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    Searched refs:RegLo (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 2471 int64_t RegLo, RegHi;
2478 if (!parseExpr(RegLo))
2486 RegHi = RegLo;
2492 if (!isUInt<32>(RegLo)) {
2502 if (RegLo > RegHi) {
2507 Num = static_cast<unsigned>(RegLo);
2508 Width = (RegHi - RegLo) + 1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 7525 Register RegLo = VA.getLocReg();
7526 RegsToPass.push_back(std::make_pair(RegLo, Lo));
7528 if (RegLo == RISCV::X17) {
7538 assert(RegLo < RISCV::X31 && "Invalid register pair");
7539 Register RegHigh = RegLo + 1;
7797 Register RegLo = VA.getLocReg();
7798 assert(RegLo < RISCV::X31 && "Invalid register pair");
7799 Register RegHi = RegLo + 1;
7801 if (STI.isRegisterReservedByUser(RegLo) ||
7807 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 1700 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1702 MIB.addReg(RegLo, Flags);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 1908 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1918 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1919 .addReg(RegLo)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 4049 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
4051 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);

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