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    Searched refs:RegNum (Results 1 - 25 of 45) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCRegisterInfo.cpp 68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
74 DwarfLLVMRegPair Key = { RegNum, 0 };
76 if (I == M+Size || I->FromReg != RegNum)
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
88 DwarfLLVMRegPair Key = { RegNum, 0 };
90 if (I != M + Size && I->FromReg == RegNum)
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true))
106 return RegNum;
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const
    [all...]
  /src/sys/external/bsd/compiler_rt/dist/lib/xray/
xray_mips.cc 34 enum RegNum : uint32_t {
105 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
107 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr);
111 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
113 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
115 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0)
    [all...]
xray_mips64.cc 35 enum RegNum : uint32_t {
105 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8);
107 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0);
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr);
111 encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9,
114 PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCCallingConv.cpp 42 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
46 // allocated yet. RegNum is actually an index into ArgRegs, which means we
47 // need to skip a register if RegNum is odd.
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
49 State.AllocateReg(ArgRegs[RegNum]);
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
68 int RegsLeft = NumArgRegs - RegNum;
72 if (RegNum != NumArgRegs && RegsLeft < 4) {
74 State.AllocateReg(ArgRegs[RegNum + i])
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  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFDebugFrame.cpp 33 unsigned RegNum) {
35 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(RegNum, IsEH)) {
42 OS << "reg" << RegNum;
63 UnwindLocation UnwindLocation::createIsRegisterPlusOffset(uint32_t RegNum,
65 return {RegPlusOffset, RegNum, Offset, false};
67 UnwindLocation UnwindLocation::createAtRegisterPlusOffset(uint32_t RegNum,
69 return {RegPlusOffset, RegNum, Offset, true};
103 printRegister(OS, MRI, IsEH, RegNum);
138 return RegNum == RHS.RegNum && Offset == RHS.Offset &
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiRegisterInfo.h 47 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
AVRInstPrinter.cpp 89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum,
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo);
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
98 return getRegisterName(RegNum);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/
AVRAsmParser.cpp 206 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
208 return std::make_unique<AVROperand>(RegNum, S, E);
217 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
218 return std::make_unique<AVROperand>(RegNum, Val, S, E);
338 int RegNum = matchFn(Name);
344 if (RegNum == AVR::NoRegister) {
345 RegNum = matchFn(Name.lower());
347 if (RegNum == AVR::NoRegister) {
348 RegNum = matchFn(Name.upper());
351 return RegNum;
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
DWARFDebugFrame.h 65 uint32_t RegNum; /// The register number for Kind == RegPlusOffset.
75 : Kind(K), RegNum(InvalidRegisterNumber), Offset(0), Dereference(false) {}
78 : Kind(K), RegNum(Reg), Offset(Off), Dereference(Deref) {}
81 : Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E),
120 uint32_t getRegister() const { return RegNum; }
126 void setRegister(uint32_t NewRegNum) { RegNum = NewRegNum; }
168 /// Return the location for the register in \a RegNum if there is a location.
170 /// \param RegNum the register number to find a location for.
172 /// \returns A location if one is available for \a RegNum, or llvm::None
174 Optional<UnwindLocation> getRegisterLocation(uint32_t RegNum) const
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp 207 unsigned RegNum;
254 return Reg.RegNum;
433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
435 Op->Reg.RegNum = RegNum;
1779 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1780 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1782 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1787 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/
MSP430AsmParser.cpp 198 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S,
200 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E);
208 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum,
211 return std::make_unique<MSP430Operand>(RegNum, Val, S, E);
214 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S,
216 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E);
219 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S,
221 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
LanaiAsmParser.cpp 69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
123 unsigned RegNum;
158 return Reg.RegNum;
594 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start,
597 Op->Reg.RegNum = RegNum;
698 unsigned RegNum;
705 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier());
706 if (RegNum == 0) {
712 return LanaiOperand::createReg(RegNum, Start, End)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/
M68kMCCodeEmitter.cpp 154 unsigned RegNum = MCO.getReg();
159 uint32_t Val = RI->getEncodingValue(RegNum);
166 Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 348 unsigned RegNum;
374 unsigned RegNum;
580 return Reg.RegNum;
590 return VectorList.RegNum;
1087 Reg.RegNum) ||
1089 Reg.RegNum));
1164 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
1169 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
1175 Reg.RegNum);
1181 Reg.RegNum);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
VEAsmParser.cpp 173 unsigned RegNum;
346 return Reg.RegNum;
596 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S,
599 Op->Reg.RegNum = RegNum;
647 Op.Reg.RegNum = I32Regs[regIdx];
656 Op.Reg.RegNum = F32Regs[regIdx];
665 Op.Reg.RegNum = F128Regs[regIdx / 2];
674 Op.Reg.RegNum = VM512Regs[regIdx / 2];
686 Op.Reg.RegNum = MISCRegs[regIdx]
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  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 513 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
517 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
521 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
525 int getSEHRegNum(MCRegister RegNum) const;
529 int getCodeViewRegNum(MCRegister RegNum) const;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
InstructionSelectorImpl.h 903 int64_t RegNum = MatchTable[CurrentIdx++];
905 OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
908 << InsnID << "], " << RegNum << ")\n");
914 int64_t RegNum = MatchTable[CurrentIdx++];
916 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
919 << InsnID << "], " << RegNum << ")\n");
925 int64_t RegNum = MatchTable[CurrentIdx++];
928 OutMIs[InsnID].addReg(RegNum, RegFlags);
932 << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/
ARCDisassembler.cpp 280 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
282 if (30 == RegNum) {
287 return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 90 unsigned RegNum;
150 return Reg.RegNum;
209 Op->Reg.RegNum = RegNo;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCInstPrinter.h 26 const char *getVerboseConditionRegName(unsigned RegNum,
PPCInstPrinter.cpp 608 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
613 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 238 unsigned RegNum;
324 return Reg.RegNum;
438 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
441 Op->Reg.RegNum = RegNum;
471 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
482 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
505 Op.Reg.RegNum = Reg;
518 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
StackMaps.cpp 179 int RegNum = TRI->getDwarfRegNum(Reg, false);
180 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
181 RegNum = TRI->getDwarfRegNum(*SR, false);
183 assert(RegNum >= 0 && "Invalid Dwarf register number.");
184 return (unsigned)RegNum;
633 /// uint16 : Dwarf RegNum
639 /// uint16 : Dwarf RegNum
  /src/external/apache2/llvm/dist/clang/lib/Basic/
TargetInfo.cpp 519 if (AN == Name && ARN.RegNum < Names.size())
560 if (AN == Name && ARN.RegNum < Names.size())
561 return ReturnCanonical ? Names[ARN.RegNum] : Name;
  /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/
CSKYAsmParser.cpp 91 unsigned RegNum;
198 return Reg.RegNum;
236 Op->Reg.RegNum = RegNo;

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