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    Searched refs:RegOp1 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 96 unsigned RegOp1 = Inst.getOperand(1).getReg();
99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
116 Inst.getOperand(0).setReg(RegOp1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 990 MachineOperand RegOp1 = getLdStRegOp(*Rt2MI);
999 RegOp1.setIsKill(false);
1019 .add(RegOp1)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 4038 Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4039 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
4041 Src1.setReg(RegOp1);

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