HomeSort by: relevance | last modified time | path
    Searched refs:RegPressure (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 60 RegPressure.resize(NumRC);
62 std::fill(RegPressure.begin(), RegPressure.end(), 0);
369 if ((RegPressure[RC->getID()] +
371 (RegPressure[RC->getID()] +
484 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID());
495 if (RegPressure[RC->getID()] >
497 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID());
498 else RegPressure[RC->getID()] = 0;
ScheduleDAGRRList.cpp 100 cl::desc("Disable regpressure priority in sched=list-ilp"));
1744 /// RegPressure - Tracking current reg pressure per register class.
1745 std::vector<unsigned> RegPressure;
1764 RegPressure.resize(NumRC);
1766 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1789 std::fill(RegPressure.begin(), RegPressure.end(), 0);
2078 unsigned RP = RegPressure[Id];
2104 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]
    [all...]
SelectionDAGISel.cpp 267 if (TLI->getSchedulingPreference() == Sched::RegPressure)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h 50 /// RegPressure - Tracking current reg pressure per register class.
52 std::vector<unsigned> RegPressure;
MachineScheduler.h 310 /// Return true if this DAG supports VReg liveness and RegPressure.
384 /// machine instructions while updating LiveIntervals and tracking regpressure.
407 IntervalPressure RegPressure;
431 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
436 /// Return true if this DAG supports VReg liveness and RegPressure.
451 const IntervalPressure &getRegPressure() const { return RegPressure; }
TargetLowering.h 100 RegPressure, // Scheduling for lowest register pressure.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineLICM.cpp 145 SmallVector<unsigned, 8> RegPressure;
186 RegPressure.clear();
353 RegPressure.resize(NumRPS);
354 std::fill(RegPressure.begin(), RegPressure.end(), 0);
666 BackTrace.push_back(RegPressure);
788 std::fill(RegPressure.begin(), RegPressure.end(), 0);
811 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
812 RegPressure[Class] = 0
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 47 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 52 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 351 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1532 setSchedulingPreference(Sched::RegPressure);
1869 return Sched::RegPressure;
1880 return Sched::RegPressure;
1888 return Sched::RegPressure;
1893 return Sched::RegPressure;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 512 setSchedulingPreference(Sched::RegPressure);
SIISelLowering.cpp 851 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 124 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 136 setSchedulingPreference(Sched::RegPressure);
    [all...]

Completed in 115 milliseconds