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    Searched refs:RegSeq (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1258 SDValue RegSeq = createQTuple(Regs);
1263 Ops.push_back(RegSeq);
1495 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1497 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1514 SDValue RegSeq = createZTuple(Regs);
1523 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
1559 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1561 SDValue Ops[] = {RegSeq,
1618 SDValue RegSeq = createQTuple(Regs);
1625 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1708 auto RegSeq =
1711 RegSeq.addReg(Zero).addImm(Sub);
1717 auto RegSeq =
1720 RegSeq.addReg(Undef).addImm(Sub);
1721 RegSeq.addReg(Zero).addImm(Parts.back());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 4636 auto RegSeq = MIB.buildInstr(TargetOpcode::REG_SEQUENCE,
4643 {RegSeq, IndexLoad->getOperand(0)});
4644 constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 2338 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2342 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2359 Ops.push_back(RegSeq);

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