| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRExpandPseudoInsts.cpp | 155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
196 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
236 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
246 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
284 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
288 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
341 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
349 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)
[all...] |
| AVRFrameLowering.cpp | 72 .addReg(AVR::R1R0, RegState::Kill)
79 .addReg(AVR::R0, RegState::Kill)
82 .addReg(AVR::R0, RegState::Define)
83 .addReg(AVR::R0, RegState::Kill)
84 .addReg(AVR::R0, RegState::Kill)
122 .addReg(AVR::R29R28, RegState::Kill)
149 .addReg(AVR::R0, RegState::Kill);
204 .addReg(AVR::R29R28, RegState::Kill)
211 .addReg(AVR::R29R28, RegState::Kill);
360 .addReg(AVR::R31R30, RegState::Kill
[all...] |
| AVRRegisterInfo.cpp | 201 .addReg(DstReg, RegState::Kill)
229 .addReg(AVR::R29R28, RegState::Kill)
236 .addReg(AVR::R0, RegState::Kill);
241 .addReg(AVR::R29R28, RegState::Kill)
|
| AVRRelaxMemOperations.cpp | 104 .addReg(Ptr.getReg(), RegState::Define)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 40 namespace RegState {
67 } // end namespace RegState
102 flags & RegState::Define,
103 flags & RegState::Implicit,
104 flags & RegState::Kill,
105 flags & RegState::Dead,
106 flags & RegState::Undef,
107 flags & RegState::EarlyClobber,
109 flags & RegState::Debug,
110 flags & RegState::InternalRead
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 108 .addReg(ScratchOffset, RegState::Kill)
115 .addReg(ScratchOffset, RegState::Kill)
121 .addReg(ScratchOffset, RegState::Kill);
184 .addReg(ScratchBase, RegState::Kill)
185 .addReg(ScratchOffset, RegState::Kill)
191 .addReg(ScratchBase, RegState::Kill)
192 .addReg(ScratchOffset, RegState::Kill)
197 .addReg(ScratchBase, RegState::Kill)
198 .addReg(ScratchOffset, RegState::Kill);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFormMemoryClauses.cpp | 136 S |= RegState::Implicit;
138 S |= RegState::Dead;
140 S |= RegState::Undef;
142 S |= RegState::Kill;
144 S |= RegState::EarlyClobber;
146 S |= RegState::Renamable;
358 KillOps.emplace_back(R.second.first | RegState::Kill,
377 KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
|
| SILateBranchLowering.cpp | 75 .addReg(AMDGPU::VGPR0, RegState::Undef)
76 .addReg(AMDGPU::VGPR0, RegState::Undef)
77 .addReg(AMDGPU::VGPR0, RegState::Undef)
78 .addReg(AMDGPU::VGPR0, RegState::Undef)
|
| SIFrameLowering.cpp | 172 .addReg(TargetReg, RegState::ImplicitDefine);
306 .addReg(FlatScrInitHi, RegState::Kill);
316 .addReg(FlatScrInitLo, RegState::Kill)
474 .addReg(PreloadedScratchWaveOffsetReg, RegState::Kill);
549 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
583 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
598 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
609 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
613 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
619 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
[all...] |
| SIRegisterInfo.cpp | 195 I.addReg(TmpVGPR, RegState::ImplicitDefine);
206 I.addReg(TmpVGPR, RegState::ImplicitDefine);
228 .addReg(SavedExecReg, RegState::Kill);
232 I.addReg(TmpVGPR, RegState::ImplicitKill);
240 I.addReg(TmpVGPR, RegState::ImplicitKill);
707 .addReg(OffsetReg, RegState::Kill)
713 .addReg(OffsetReg, RegState::Kill)
1173 MIB.addReg(ValueReg, RegState::ImplicitDefine);
1180 State &= ~RegState::Kill;
1181 MIB.addReg(ValueReg, RegState::Implicit | State)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 92 .addReg(ScratchReg, RegState::Kill)
415 .addReg(ARM::SP, RegState::Kill)
420 .addReg(ARM::R4, RegState::Kill)
426 .addReg(ARM::R4, RegState::Kill)
431 .addReg(ARM::R4, RegState::Kill)
646 MIB.addReg(ARM::PC, RegState::Define);
724 .addReg(PopReg, RegState::Define)
730 .addReg(ARM::LR, RegState::Define)
731 .addReg(PopReg, RegState::Kill)
746 .addReg(TemporaryReg, RegState::Define
[all...] |
| ARMExpandPseudoInsts.cpp | 556 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
560 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
562 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
564 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
566 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
627 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
703 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
747 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
749 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
751 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead))
[all...] |
| ARMFrameLowering.cpp | 378 .addReg(Reg, RegState::Kill)
383 .addReg(Reg, RegState::Kill)
393 .addReg(Reg, RegState::Kill)
398 .addReg(Reg, RegState::Kill)
408 .addReg(Reg, RegState::Kill)
629 .addReg(ARM::R4, RegState::Implicit)
639 .addReg(ARM::R12, RegState::Kill)
640 .addReg(ARM::R4, RegState::Implicit)
646 .addReg(ARM::SP, RegState::Kill)
647 .addReg(ARM::R4, RegState::Kill
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86PreTileConfig.cpp | 363 .addReg(Zmm, RegState::Undef)
364 .addReg(Zmm, RegState::Undef);
370 .addReg(Ymm, RegState::Undef)
371 .addReg(Ymm, RegState::Undef);
380 .addReg(Xmm, RegState::Undef)
381 .addReg(Xmm, RegState::Undef);
|
| X86LoadValueInjectionRetHardening.cpp | 85 .addReg(ClobberReg, RegState::Define)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCFrameLowering.cpp | 149 .addReg(ARC::SP, RegState::Define)
166 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
296 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
313 .addReg(ARC::FP, RegState::Define)
314 .addReg(ARC::SP, RegState::Define)
463 .addReg(Reg, RegState::Kill)
|
| ARCRegisterInfo.cpp | 76 .addReg(BaseReg, RegState::Define)
80 KillState = RegState::Kill;
116 .addReg(Reg, RegState::Define)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 93 MIB.addReg(DestReg, RegState::Define);
265 addSaveRestoreRegs(MIB, CSI, RegState::Define);
267 MIB.addReg(Mips::S2, RegState::Define);
290 MIB2.addReg(Mips::SP, RegState::Kill);
293 MIB3.addReg(Reg2, RegState::Kill);
296 MIB4.addReg(Reg1, RegState::Kill);
418 .addReg(SpReg, RegState::Kill)
423 .addReg(Reg, RegState::Kill);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 124 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0;
158 .addReg(DstReg, RegState::Define |
170 RegState::Define |
226 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
297 .addReg(DestLo.getReg(), RegState::Define)
298 .addReg(DestHi.getReg(), RegState::Define)
313 .addUse(StatusReg, RegState::Kill)
314 .addUse(StatusReg, RegState::Kill)
515 .addReg(DstReg, RegState::Define
[all...] |
| AArch64SpeculationHardening.cpp | 399 .addDef(TmpReg, RegState::Renamable)
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable)
401 .addUse(MisspeculatingTaintReg, RegState::Kill)
406 .addUse(TmpReg, RegState::Kill)
578 .addUse(SrcReg, RegState::Kill)
|
| AArch64FrameLowering.cpp | 962 MIB.addReg(AArch64::SP, RegState::Define);
1340 .addReg(AArch64::X15, RegState::Implicit)
1341 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1342 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
1343 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 649 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
652 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
658 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
768 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
808 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
833 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
845 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 589 .addReg(Reg, RegState::Kill)
597 .addReg(Reg, RegState::Kill)
680 .addReg(NegSizeReg1, RegState::Kill);
697 .addReg(NegSizeReg1, RegState::Kill);
806 .addReg(Reg1, RegState::Kill)
813 .addReg(Reg, RegState::Kill),
852 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
857 .addReg(Reg, RegState::Kill);
929 .addReg(SrcReg, RegState::Undef);
943 .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterInfo.cpp | 242 .addReg(ScratchReg, RegState::Kill);
248 .addReg(ScratchReg, RegState::Kill);
280 .addReg(ScalableFactorRegister, RegState::Kill);
287 .addReg(ScalableFactorRegister, RegState::Kill);
|
