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    Searched refs:RegUnit (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterPressure.cpp 100 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
155 void RegPressureTracker::increaseRegPressure(Register RegUnit,
161 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
170 void RegPressureTracker::decreaseRegPressure(Register RegUnit,
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);
363 Register RegUnit = Pair.RegUnit;
364 if (Register::isVirtualRegister(RegUnit)
365 && !RPTracker.hasUntiedDef(RegUnit))
    [all...]
LiveRegMatrix.cpp 179 MCRegister RegUnit) {
180 LiveIntervalUnion::Query &Q = Queries[RegUnit];
181 Q.init(UserTag, LR, Matrix[RegUnit]);
MachineCopyPropagation.cpp 178 MachineInstr *findCopyForUnit(MCRegister RegUnit,
181 auto CI = Copies.find(RegUnit);
189 MachineInstr *findCopyDefViaUnit(MCRegister RegUnit,
191 auto CI = Copies.find(RegUnit);
223 // We check the first RegUnit here, since we'll only be interested in the
MachineTraceMetrics.cpp 698 // Identify physreg dependencies for UseMI, and update the live regunit
927 // This regunit is dead above MI.
1020 // Instead, keep track of the highest use of each regunit.
1111 // There may also be regunit dependencies to include in the height.
1144 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
1145 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@'
MachineScheduler.cpp 1118 Register Reg = P.RegUnit;
1343 Register Reg = P.RegUnit;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterPressure.h 40 Register RegUnit; ///< Virtual register or register unit.
43 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
44 : RegUnit(RegUnit), LaneMask(LaneMask) {}
160 void addPressureChange(Register RegUnit, bool IsDec,
306 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
319 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
551 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
553 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
564 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
    [all...]
LiveRegMatrix.h 18 // the virtual register is inserted into the LiveIntervalUnion for each regunit
142 /// Check for regunit interference only.
151 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
153 /// Directly access the live interval unions per regunit.
154 /// This returns an array indexed by the regunit number.
MachineTraceMetrics.h 72 // Associate each regunit with an instruction operand. Depending on the
74 // regunit, or the highest operand to read the regunit.
76 unsigned RegUnit;
81 unsigned getSparseSetIndex() const { return RegUnit; }
83 LiveRegUnit(unsigned RU) : RegUnit(RU) {}
139 /// A virtual register or regunit required by a basic block or its trace
MachineRegisterInfo.h 623 /// virtual register. If RegUnit is physical, it must be a register unit (from
625 PSetIterator getPressureSets(Register RegUnit) const;
1199 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1201 if (RegUnit.isVirtual()) {
1202 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1206 PSet = TRI->getRegUnitPressureSets(RegUnit);
1207 Weight = TRI->getRegUnitWeight(RegUnit);
1228 MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1229 return PSetIterator(RegUnit, this);
TargetRegisterInfo.h 432 /// Returns true if Reg contains RegUnit.
433 bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
435 if (Register(*Units) == RegUnit)
810 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
830 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 484 struct RegUnit {
485 // Weight assigned to this RegUnit for estimating register pressure.
490 // Each native RegUnit corresponds to one or two root registers. The full
502 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) {
553 SmallVector<RegUnit, 8> RegUnits;
567 // class's units and any inferred RegUnit supersets.
684 RegUnit &RU = RegUnits.back();
712 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
713 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
CodeGenRegisters.cpp 428 // Create a RegUnit representing this alias edge, and add it to both
587 for (unsigned RegUnit : RegUnits) {
588 Weight += RegBank.getRegUnit(RegUnit).Weight;
1089 const RegUnit &RU = RegBank.getRegUnit(*UnitI);
RegisterInfoEmitter.cpp 243 << "getRegUnitWeight(unsigned RegUnit) const {\n"
244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
251 assert(RU.Weight < 256 && "RegUnit too heavy");
255 << " return RUWeightTable[RegUnit];\n";
340 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
341 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
351 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
626 // Differentially encoded register and regunit lists allow for better
977 // Emit the shared table of regunit lane mask sequences
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNRegPressure.cpp 232 Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; });
312 auto LiveMask = LiveRegs[U.RegUnit];
313 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
334 auto &LiveMask = LiveRegs[U.RegUnit];
337 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
SIOptimizeExecMaskingPreRA.cpp 285 LiveRange &RegUnit = LIS->getRegUnit(*UI);
286 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))
SIMachineScheduler.h 469 InRegs.insert(RegMaskPair.RegUnit);
477 OutRegs.insert(RegMaskPair.RegUnit);
SIRegisterInfo.h 258 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
SIWholeQuadMode.cpp 457 for (MCRegUnitIterator RegUnit(Reg.asMCReg(), TRI); RegUnit.isValid();
458 ++RegUnit) {
459 LiveRange &LR = LIS->getRegUnit(*RegUnit);
464 markDefs(MI, LR, *RegUnit, AMDGPU::NoSubRegister, Flag, Worklist);
SIMachineScheduler.cpp 332 if (Register::isVirtualRegister(RegMaskPair.RegUnit))
333 LiveInRegs.insert(RegMaskPair.RegUnit);
359 Register Reg = RegMaskPair.RegUnit;
SIRegisterInfo.cpp 2311 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
2314 if (RegPressureIgnoredUnits[RegUnit])
2317 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
193 /// differentially encoded register and regunit lists in DiffLists.
721 /// Returns a (RegUnit, LaneMask) pair.
753 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
754 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
755 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
756 Reg1 = MCRI->RegUnitRoots[RegUnit][1];

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