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    Searched refs:RegVT (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CallingConvLower.cpp 254 for (MVT RegVT : RegParmTypes) {
256 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn);
258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SwitchLoweringUtils.h 213 MVT RegVT;
227 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 322 EVT RegVT = VA.getLocVT();
323 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
327 << RegVT.getEVTString() << '\n';
335 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
343 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1149 EVT RegVT = VA.getLocVT();
1151 if (RegVT == MVT::i8) {
1153 } else if (RegVT == MVT::i16) {
1160 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1182 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1281 EVT RegVT = VA.getLocVT();
1291 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1294 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1297 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 484 EVT RegVT = VA.getLocVT();
485 switch (RegVT.getSimpleVT().SimpleTy) {
488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
494 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 460 EVT RegVT = VA.getLocVT();
461 switch (RegVT.getSimpleVT().SimpleTy) {
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
485 << RegVT.getEVTString() << "\n");
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 592 EVT RegVT = VA.getLocVT();
603 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
606 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
609 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
612 Arg = DAG.getBitcast(RegVT, Arg);
893 EVT RegVT = VA.getLocVT();
895 if (RegVT == MVT::i32)
901 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
910 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 642 EVT RegVT = VA.getLocVT();
643 switch (RegVT.getSimpleVT().SimpleTy) {
648 << RegVT.getEVTString() << "\n";
655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 841 MVT RegVT = VA.getLocVT();
843 RegVT = VA.getValVT();
845 const TargetRegisterClass *RC = getRegClassFor(RegVT);
847 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
853 assert(RegVT.getSizeInBits() <= 32);
854 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
855 Copy, DAG.getConstant(1, dl, RegVT));
856 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
860 unsigned RegSize = RegVT.getSizeInBits();
862 Subtarget.isHVXVectorType(RegVT));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1301 EVT RegVT = VA.getLocVT();
1302 switch (RegVT.getSimpleVT().SimpleTy) {
1307 << RegVT.getEVTString() << "\n";
1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 893 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
894 Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
IRTranslator.cpp 1017 B.RegVT = getMVTForLLT(MaskTy);
1049 LLT SwitchTy = getLLTForMVT(BB.RegVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 3664 MVT RegVT = VA.getLocVT();
3666 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3671 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3677 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3678 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3679 (RegVT == MVT::f64 && ValVT == MVT::i64))
3681 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3685 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 5363 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5367 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5373 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5375 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5380 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5382 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5415 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5438 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5441 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5448 RegVT));
    [all...]
PPCISelDAGToDAG.cpp 700 EVT RegVT = ST->getValue().getValueType();
707 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
711 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
715 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
745 EVT RegVT = LD->getValueType(0);
751 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
755 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
759 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 777 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
779 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
2774 B.RegVT = VT.getSimpleVT();
2775 B.Reg = FuncInfo.CreateReg(B.RegVT);
2813 MVT VT = BB.RegVT;
8232 const MVT RegVT = *TRI.legalclasstypes_begin(*RC);
8248 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
8254 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
8255 OpInfo.ConstraintVT = RegVT;
8259 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint())
    [all...]
TargetLowering.cpp 7395 EVT RegVT = Value.getValueType();
7396 EVT RegSclVT = RegVT.getScalarType();
7493 MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
7495 unsigned RegBytes = RegVT.getSizeInBits() / 8;
7499 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
7515 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
7533 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
7643 MVT RegVT = getRegisterType(
7648 unsigned RegBytes = RegVT.getSizeInBits() / 8;
7652 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT);
    [all...]
LegalizeIntegerTypes.cpp 1423 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1425 // The argument is passed as NumRegs registers of type RegVT.
1429 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1445 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 3658 EVT RegVT = VA.getLocVT();
3670 if (RegVT == MVT::i8)
3672 else if (RegVT == MVT::i16)
3674 else if (RegVT == MVT::i32)
3676 else if (Is64Bit && RegVT == MVT::i64)
3678 else if (RegVT == MVT::f32)
3680 else if (RegVT == MVT::f64)
3682 else if (RegVT == MVT::f80)
3684 else if (RegVT == MVT::f128)
3686 else if (RegVT.is512BitVector()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 2871 EVT RegVT = VA.getLocVT();
2876 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2885 if (RegVT == MVT::v2f64) {
4318 EVT RegVT = VA.getLocVT();
4346 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4348 else if (RegVT == MVT::f32)
4350 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 |
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 4884 EVT RegVT = VA.getLocVT();
4887 if (RegVT == MVT::i32)
4889 else if (RegVT == MVT::i64)
4891 else if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4893 else if (RegVT == MVT::f32)
4895 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
4897 else if (RegVT == MVT::f128 || RegVT.is128BitVector()
    [all...]

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