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    Searched refs:RegVTs (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.h 846 /// With virtual registers, the contents of RegVTs is redundant with TLI's
849 SmallVector<MVT, 4> RegVTs;
877 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
SelectionDAGBuilder.cpp 779 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
800 RegVTs.push_back(RegisterVT);
825 CallConv.getValue(), RegVTs[Value])
826 : RegVTs[Value];
908 CallConv.getValue(), RegVTs[Value])
909 : RegVTs[Value];
976 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
981 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
992 MVT RegisterVT = RegVTs[Value];
1005 for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenInstruction.cpp 459 const std::vector<ValueTypeByHwMode> &RegVTs =
461 if (RegVTs.size() == 1 && RegVTs[0].isSimple())
462 return RegVTs[0].getSimple().SimpleTy;

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