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    Searched refs:RegWidth (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AddressingModes.h 809 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) {
810 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
817 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) {
818 if (RegWidth == 32)
828 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) {
830 if (isAnyMOVZMovAlias(Value, RegWidth))
834 if (RegWidth == 32)
837 return isMOVZMovAlias(Value, Shift, RegWidth);
840 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) {
841 if (isAnyMOVZMovAlias(Value, RegWidth))
    [all...]
AArch64InstPrinter.cpp 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
245 << formatImm(SignExtend64(Value, RegWidth));
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
255 if (RegWidth == 32)
258 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
260 << formatImm(SignExtend64(Value, RegWidth));
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
271 MI->getOperand(2).getImm(), RegWidth);
272 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
274 << formatImm(SignExtend64(Value, RegWidth));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonTargetTransformInfo.cpp 177 unsigned RegWidth =
180 assert(RegWidth && "Non-zero vector register width expected");
182 if (VecWidth % RegWidth == 0)
183 return VecWidth / RegWidth;
185 const Align RegAlign(RegWidth / 8);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1153 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) {
1155 case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break;
1157 case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break;
1231 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1234 unsigned &RegNum, unsigned &RegWidth,
1237 unsigned &RegNum, unsigned &RegWidth,
1240 unsigned &RegWidth,
1243 unsigned &RegWidth,
1246 unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
1250 unsigned RegWidth,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 1009 template<int RegWidth, int Shift>
1017 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
1024 template<int RegWidth, int Shift>
1032 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
4796 uint64_t RegWidth = 0;
4799 RegWidth = 64;
4801 RegWidth = 32;
4803 if (LSB >= RegWidth)
4806 if (Width < 1 || Width > RegWidth)
4811 if (RegWidth == 32
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 1044 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8;
1048 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1049 unsigned NumSubRegs = RegWidth / EltSize;
1051 unsigned RemSize = RegWidth - Size;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 1489 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1490 return (BitWidth + RegWidth - 1) / RegWidth;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 6978 unsigned RegWidth = RegType.getSizeInBits();
6980 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth())
6989 auto *NewType = Type::getIntNTy(Context, RegWidth);
7007 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 316 template<unsigned RegWidth>
318 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
2855 unsigned RegWidth) {
2891 if (FBits == 0 || FBits > RegWidth) return false;

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