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    Searched refs:Regs (Results 1 - 25 of 73) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LowerHomogeneousPrologEpilog.cpp 129 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs,
147 for (auto Reg : Regs)
241 /// Return a unique function if a helper can be formed with the given Regs
268 /// @param Regs callee save regs that the helper will handle
272 SmallVectorImpl<unsigned> &Regs,
275 assert(Regs.size() >= 2);
276 auto Name = getFrameHelperName(Regs, Type, FpOffset);
286 int Size = (int)Regs.size();
292 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR))
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CallingConvLower.h 335 /// in the set, or Regs.size() if they are all allocated.
336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
337 for (unsigned i = 0; i < Regs.size(); ++i)
338 if (!isAllocated(Regs[i]))
340 return Regs.size();
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
371 unsigned FirstUnalloc = getFirstUnallocated(Regs);
372 if (FirstUnalloc == Regs.size())
376 MCPhysReg Reg = Regs[FirstUnalloc];
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired)
    [all...]
RegisterPressure.h 275 RegSet Regs;
297 RegSet::const_iterator I = Regs.find(SparseIndex);
298 if (I == Regs.end())
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
320 RegSet::iterator I = Regs.find(SparseIndex);
321 if (I == Regs.end())
329 return Regs.size();
334 for (const IndexMaskPair &P : Regs) {
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
HWEventListener.h 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs,
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {}
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs)
97 FreedPhysRegs(Regs) {}
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
SystemZDisassembler.cpp 83 const unsigned *Regs, unsigned Size) {
85 RegNo = Regs[RegNo];
292 const unsigned *Regs) {
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
302 const unsigned *Regs) {
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
312 const unsigned *Regs) {
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
324 const unsigned *Regs) {
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMUnwindOpAsm.cpp 107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
108 while (Regs) {
110 auto RangeMSB = 32 - countLeadingZeros(Regs);
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
121 Regs &= ~(-1u << RangeLSB);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 38 /// Regs - If this is a register or register class operand, this
40 SmallVector<Register, 1> Regs;
137 OpInfo.Regs.push_back(R);
399 if (OpInfo.Regs.empty()) {
410 OpInfo.Regs.size());
411 if (OpInfo.Regs.front().isVirtual()) {
416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
422 for (Register Reg : OpInfo.Regs) {
545 if (OpInfo.Regs.empty()) {
552 unsigned NumRegs = OpInfo.Regs.size()
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CallLowering.cpp 217 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
224 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
230 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
249 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
311 /// value registers of type \p LLTy, and \p Regs contains the legalized pieces
314 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
321 assert(OrigRegs[0] == Regs[0]);
326 Regs.size() == 1) {
327 B.buildBitcast(OrigRegs[0], Regs[0])
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CallLowering.h 62 SmallVector<Register, 4> Regs;
74 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
77 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
79 if (!Regs.empty() && Flags.empty())
83 (Regs.empty() || Regs[0] == 0)) &&
87 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
90 : ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {
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  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
Taint.cpp 136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap();
138 Regs = F.add(Regs, SubRegion, Kind);
139 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs);
202 if (const TaintedSubRegions *Regs =
205 for (auto I : *Regs) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
89 const std::deque<CodeGenRegister> &Regs,
107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
218 const CodeGenRegister::Vec &Regs = RC.getMembers();
220 if (Regs.empty() || RC.Artificial)
383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
389 for (auto &RE : Regs) {
405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
450 for (auto &RE : Regs) {
510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor)
    [all...]
CodeGenRegisters.cpp 209 RegUnitIterator(const CodeGenRegister::Vec &Regs):
210 RegI(Regs.begin()), RegE(Regs.end()) {
391 // SR is composed of multiple sub-regs. Find their names in this register.
1121 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1122 llvm::sort(Regs, LessRecordRegister());
1124 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1125 getReg(Regs[i]);
1580 CodeGenRegister::Vec Regs;
1609 const CodeGenRegister::Vec &Regs = RegClass.getMembers()
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  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
RegisterAliasing.cpp 82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) {
84 for (const unsigned Reg : Regs.set_bits()) {
RegisterAliasing.h 114 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 158 // Return true to make these hints the only regs available to
240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
242 return Regs->getCalleeSavedRegs(MF);
250 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
251 return Regs->getCallPreservedMask(MF, CC);
259 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
262 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true);
267 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true);
439 // Demand an arbitrary margin of free regs.
451 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 67 static SDValue createTupleImpl(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs,
69 assert(Regs.size() >= 2 && Regs.size() <= 8);
71 SDLoc DL(Regs[0]);
76 for (unsigned I = 0; I < Regs.size(); ++I) {
77 Ops.push_back(Regs[I]);
85 static SDValue createM1Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs,
92 return createTupleImpl(CurDAG, Regs, RegClassIDs[NF - 2], RISCV::sub_vrm1_0);
95 static SDValue createM2Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs,
101 return createTupleImpl(CurDAG, Regs, RegClassIDs[NF - 2], RISCV::sub_vrm2_0)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
SystemZAsmParser.cpp 865 const unsigned *Regs;
867 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
868 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
869 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
870 case GR128Reg: Regs = SystemZMC::GR128Regs; break;
871 case FP32Reg: Regs = SystemZMC::FP32Regs; break;
872 case FP64Reg: Regs = SystemZMC::FP64Regs; break;
873 case FP128Reg: Regs = SystemZMC::FP128Regs; break;
874 case VR32Reg: Regs = SystemZMC::VR32Regs; break;
875 case VR64Reg: Regs = SystemZMC::VR64Regs; break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExecutionDomainFix.cpp 329 SmallVector<int, 4> Regs;
341 auto I = partition_point(Regs, [&](int I) {
344 Regs.insert(I, rx);
350 while (!Regs.empty()) {
352 dv = LiveRegs[Regs.pop_back_val()];
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()];
AggressiveAntiDepBreaker.cpp 80 std::vector<unsigned> &Regs,
85 Regs.push_back(Reg);
155 // Examine the live-in regs of all successors.
554 std::vector<unsigned> Regs;
555 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
556 assert(!Regs.empty() && "Empty register group!");
557 if (Regs.empty())
567 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
568 unsigned Reg = Regs[i];
572 // If Reg has any references, then collect possible rename regs
    [all...]
AggressiveAntiDepBreaker.h 99 std::vector<unsigned> &Regs,
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegisterInfo.cpp 144 static const unsigned Regs[2][2] = {
149 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUPALMetadata.cpp 162 auto Regs = getRegisters();
163 auto It = Regs.find(MsgPackDoc.getNode(Reg));
164 if (It == Regs.end())
648 auto Regs = getRegisters();
649 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
650 if (I != Regs.begin())
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 59 // | callee-saved fp/simd regs |
1084 SmallVector<RegAndKill, 4> Regs;
1111 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
1114 if (Regs.empty())
1117 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) {
1121 if (Regs.size() > 1 || StrOpc== 0) {
1126 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1127 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1128 } else if (Regs.size() == 1)
    [all...]
Thumb2ITBlockPass.cpp 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100 for (unsigned Reg : Regs)
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
RegisterFile.h 279 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;

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