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    Searched refs:RequiredDPPCLK (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_mode_vba_20v2.c 3964 locals->RequiredDPPCLK[i][j][k] =
3968 locals->RequiredDPPCLK[i][j][k] =
3998 locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
4011 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
4015 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
4465 locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
4495 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4520 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4545 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4760 mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay (…)
    [all...]
amdgpu_display_mode_vba_20.c 3920 locals->RequiredDPPCLK[i][j][k] =
3924 locals->RequiredDPPCLK[i][j][k] =
3954 locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
3967 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
3971 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
4416 locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
4446 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4471 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4496 * mode_lib->vba.RequiredDPPCLK[i][j][k]);
4711 mode_lib->vba.RequiredDPPCLK[i][j][k]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 1069 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1078 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_mode_vba_21.c 4000 locals->RequiredDPPCLK[i][j][k] =
4004 locals->RequiredDPPCLK[i][j][k] =
4034 locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
4047 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
4051 locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
4412 locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
4705 myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k];
5204 locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
display_mode_vba.h 508 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 2539 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2621 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2678 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2687 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];

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