| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 358 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
360 ResultReg)
364 return ResultReg;
381 unsigned ResultReg = createResultReg(RC);
383 ResultReg).addReg(ZeroReg, getKillRegState(true));
384 return ResultReg;
417 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
419 TII.get(TargetOpcode::COPY), ResultReg)
422 return ResultReg;
435 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT))
[all...] |
| AArch64InstrInfo.cpp | 5014 Register ResultReg = Root.getOperand(0).getReg();
5031 if (Register::isVirtualRegister(ResultReg))
5032 MRI.constrainRegClass(ResultReg, RC);
5042 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
5047 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
5053 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
5165 Register ResultReg = Root.getOperand(0).getReg();
5171 if (Register::isVirtualRegister(ResultReg))
5172 MRI.constrainRegClass(ResultReg, RC);
5181 BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 480 Register ResultReg =
483 if (!ResultReg)
487 updateValueMap(I, ResultReg);
513 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
515 if (!ResultReg)
519 updateValueMap(I, ResultReg);
528 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
530 if (!ResultReg)
536 updateValueMap(I, ResultReg);
804 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
328 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
329 if (!ResultReg)
332 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
333 return ResultReg;
344 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346 ResultReg)
349 return ResultReg;
365 unsigned ResultReg = createResultReg(RC);
369 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 88 unsigned &ResultReg, unsigned Alignment = 1);
96 unsigned &ResultReg);
323 MachineMemOperand *MMO, unsigned &ResultReg,
474 ResultReg = createResultReg(RC);
476 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
709 unsigned &ResultReg) {
714 ResultReg = RR;
1349 unsigned ResultReg = 0;
1350 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg,
1354 updateValueMap(I, ResultReg);
[all...] |
| X86InstructionSelector.cpp | 983 Register ResultReg = I.getOperand(0).getReg();
985 ResultReg,
986 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1000 TII.get(SETFOpc[2]), ResultReg)
1027 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 589 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
591 ResultReg)
593 return ResultReg;
601 unsigned ResultReg =
606 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
608 return ResultReg;
620 unsigned ResultReg =
625 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
627 return ResultReg;
718 unsigned ResultReg = createResultReg(RC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 191 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
300 Register ResultReg = createResultReg(RC);
308 ResultReg).addReg(Op0));
313 TII.get(TargetOpcode::COPY), ResultReg)
316 return ResultReg;
322 unsigned ResultReg = createResultReg(RC);
332 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
340 TII.get(TargetOpcode::COPY), ResultReg)
343 return ResultReg;
349 unsigned ResultReg = createResultReg(RC)
[all...] |
| ARMInstructionSelector.cpp | 688 auto ResultReg = MIB.getReg(0);
696 .addDef(ResultReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 161 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
431 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
433 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
434 Addr.Base.Reg = ResultReg;
450 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
457 // If ResultReg is given, it determines the register class of the load.
465 (ResultReg ? MRI.getRegClass(ResultReg) :
521 if (ResultReg == 0)
522 ResultReg = createResultReg(UseRC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 6077 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6091 MRI.replaceRegWith(OldDstReg, ResultReg);
6094 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6158 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6161 BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg)
6168 MRI.replaceRegWith(Dest.getReg(), ResultReg);
6170 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6183 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6192 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
6196 MRI.replaceRegWith(Dest.getReg(), ResultReg);
[all...] |
| SIRegisterInfo.cpp | 1737 Register ResultReg =
1744 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1748 if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
1749 // Reuse ResultReg in intermediate step.
1750 Register ScaledReg = ResultReg;
1800 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1819 FIOp.ChangeToRegister(ResultReg, false, false, true);
|
| SIISelLowering.cpp | 3496 unsigned InitReg, unsigned ResultReg, unsigned PhiReg,
3514 .addReg(ResultReg)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| FastISel.h | 90 Register ResultReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| MachineIRBuilder.cpp | 719 for (unsigned ResultReg : ResultRegs)
720 MIB.addDef(ResultReg);
|
| LegalizerHelper.cpp | 1360 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1375 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1376 ResultReg = NextResult;
1380 MIRBuilder.buildTrunc(DstReg, ResultReg);
1382 MIRBuilder.buildIntToPtr(DstReg, ResultReg);
6159 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0);
6172 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
6173 ResultReg = NextResult;
6183 MIRBuilder.buildIntToPtr(DstReg, ResultReg);
|
