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    Searched refs:ResultRegs (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 4398 SmallVector<Register, 5> ResultRegs(ResultNumRegs, Dst1Reg);
4404 ResultRegs[0] = NewResultReg;
4408 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy);
4409 B.buildUnmerge(ResultRegs, NewResultReg);
4414 ResultRegs.resize(NumDataRegs);
4420 B.buildTrunc(DstReg, ResultRegs[0]);
4426 B.buildBitcast(DstReg, ResultRegs[0]);
4439 for (Register &Reg : ResultRegs)
4442 for (Register &Reg : ResultRegs)
4452 ResultRegs.push_back(Undef)
    [all...]
AMDGPURegisterBankInfo.cpp 709 SmallVector<Register, 4> ResultRegs;
743 ResultRegs.push_back(Def.getReg());
793 for (auto Result : zip(InitResultRegs, ResultRegs, PhiRegs)) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 714 ArrayRef<Register> ResultRegs,
719 for (unsigned ResultReg : ResultRegs)
LegalizerHelper.cpp 4005 SmallVector<Register, 8> ResultRegs[2];
4041 ResultRegs[J].push_back(Inst.getReg(J));
4050 ResultRegs[I].append(NumUndefParts, Undef);
4062 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs[I]);
4487 Register ResultRegs[2];
4505 ResultRegs[0] = Lo.getReg(0);
4506 ResultRegs[1] = Hi.getReg(0);
4534 ResultRegs[0] = Lo.getReg(0);
4535 ResultRegs[1] = Hi.getReg(0);
4542 MIRBuilder.buildMerge(DstReg, ResultRegs);
    [all...]
IRTranslator.cpp 2297 ArrayRef<Register> ResultRegs;
2299 ResultRegs = getOrCreateVRegs(CI);
2304 MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());

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