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    Searched refs:RetRegs (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLegalizerInfo.cpp 386 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
388 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy},
ARMFastISel.cpp 2089 SmallVector<unsigned, 4> RetRegs;
2150 RetRegs.push_back(VA.getLocReg());
2165 for (unsigned R : RetRegs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1700 SmallVector<unsigned, 4> RetRegs;
1733 RetRegs.push_back(RetReg);
1746 RetRegs.push_back(VA.getLocReg());
1788 TII.get(TargetOpcode::COPY), RetRegs[i])
1797 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1798 MIB.addReg(RetRegs[i], RegState::Implicit);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 1688 SmallVector<unsigned, 4> RetRegs;
1769 RetRegs.push_back(VA.getLocReg());
1772 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1773 MIB.addReg(RetRegs[i], RegState::Implicit);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 1209 SmallVector<unsigned, 4> RetRegs;
1279 RetRegs.push_back(VA.getLocReg());
1297 RetRegs.push_back(RetReg);
1310 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1311 MIB.addReg(RetRegs[i], RegState::Implicit);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 3767 SmallVector<unsigned, 4> RetRegs;
3845 RetRegs.push_back(VA.getLocReg());
3850 for (unsigned RetReg : RetRegs)

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