| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RuntimeLibcalls.h | 38 Libcall getFPEXT(EVT OpVT, EVT RetVT);
42 Libcall getFPROUND(EVT OpVT, EVT RetVT);
46 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
50 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
54 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
58 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
|
| FastISel.h | 346 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
350 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0);
354 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
360 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
373 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
378 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
434 Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx);
|
| TargetLowering.h | 3243 EVT RetVT, ArrayRef<SDValue> Ops,
3896 MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT,
3899 RetVTBeforeSoften = RetVT;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 216 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
218 if (RetVT == MVT::f32)
220 if (RetVT == MVT::f64)
222 if (RetVT == MVT::f128)
225 if (RetVT == MVT::f64)
227 if (RetVT == MVT::f128)
229 if (RetVT == MVT::ppcf128)
232 if (RetVT == MVT::f128)
234 else if (RetVT == MVT::ppcf128)
237 if (RetVT == MVT::f128
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
214 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
222 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
223 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
224 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
233 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS
[all...] |
| AArch64ISelLowering.cpp | 15731 const EVT RetVT = N->getValueType(0);
15732 assert(RetVT.isScalableVector() &&
15738 if (RetVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
15753 RetVT.getScalarSizeInBits());
15775 RetVT.getScalarSizeInBits() / 8)) {
15801 EVT HwRetVt = getSVEContainerType(RetVT);
15806 SDValue OutVT = DAG.getValueType(RetVT);
15807 if (RetVT.isFloatingPoint())
15818 if (RetVT.isInteger() && (RetVT != HwRetVt)
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 518 MVT::SimpleValueType RetVT = MVT::isVoid;
519 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getSimpleType(0);
520 MVT::SimpleValueType VT = RetVT;
592 [RetVT].count(PredicateCheck)) {
596 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
601 SimplePatterns[Operands][OpcodeName][VT][RetVT].emplace(complexity,
711 MVT::SimpleValueType RetVT = RI.first;
716 << getLegalCName(std::string(getName(RetVT))) << "_";
722 emitInstructionCode(OS, Operands, PM, std::string(getName(RetVT)));
729 OS << "(MVT RetVT";
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 192 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
1488 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1499 if (RetVT != MVT::isVoid) {
1502 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1512 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1518 if (RetVT == CopyVT) {
1524 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1532 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 226 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2017 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2027 if (RetVT != MVT::isVoid) {
2030 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2033 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2054 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2202 MVT RetVT;
2204 RetVT = MVT::isVoid
[all...] |
| ARMISelLowering.cpp | 3029 auto RetVT = Outs[realRVLocIdx].ArgVT;
3030 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3035 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 119 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
121 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
123 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
244 MVT RetVT;
248 if (!isTypeLegal(RetTy, RetVT))
251 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2033 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
2039 if (RetVT < MVT::i16 || RetVT > MVT::i64
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 201 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
246 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
295 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1276 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1280 if (RetVT != MVT::isVoid) {
1294 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1512 MVT RetVT;
1514 RetVT = MVT::isVoid
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 1995 EVT RetVT = Node->getValueType(0);
1996 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2015 bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2055 EVT RetVT = Node->getValueType(0);
2059 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2111 EVT RetVT = Node->getValueType(0);
2115 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2149 EVT RetVT = Node->getValueType(0);
2150 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2165 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
[all...] |
| LegalizeFloatTypes.cpp | 919 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted,
927 if (Promoted.bitsGE(RetVT))
1992 EVT RetVT = N->getOperand(0).getValueType();
1994 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2005 EVT RetVT = N->getOperand(0).getValueType();
2007 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2018 EVT RetVT = N->getOperand(0).getValueType();
2020 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2031 EVT RetVT = N->getOperand(0).getValueType();
2033 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
[all...] |
| FastISel.cpp | 2100 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
2102 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
|
| TargetLowering.cpp | 146 /// result of type RetVT.
148 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
180 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
182 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt);
405 EVT RetVT = getCmpLibcallReturnType();
410 CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true);
411 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain);
413 NewRHS = DAG.getConstant(0, dl, RetVT);
417 assert(RetVT.isInteger());
418 CCCode = getSetCCInverse(CCCode, RetVT);
[all...] |
| LegalizeVectorTypes.cpp | 5150 EVT RetVT = WidenEltVT;
5152 return RetVT;
5174 RetVT = MemVT;
5197 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT)
5205 return RetVT;
|
| LegalizeIntegerTypes.cpp | 2232 EVT RetVT = Node->getValueType(0);
2244 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
3141 EVT RetVT = N->getValueType(0);
3146 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
|
| SelectionDAGBuilder.cpp | 6251 EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6252 setValue(&I, DAG.getNode(Opcode, sdl, RetVT,
9366 EVT RetVT = OldRetTys[i];
9368 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
9369 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 1155 EVT RetVT = TLI.getValueType(DL, I->getType());
1156 if (!VT.isSimple() || !RetVT.isSimple())
1163 if (VT == RetVT) {
1169 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
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