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    Searched refs:Rm (Results 1 - 25 of 25) sorted by relevancy

  /src/sys/arch/sh3/include/
locore.h 169 #define __EXCEPTION_BLOCK(Rn, Rm) ;\
173 stc sr, Rm ;\
174 or Rm, Rn ;\
177 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\
181 stc sr, Rm ;\
182 and Rn, Rm ;\
183 ldc Rm, sr /* unblock exceptions */
189 #define __INTR_MASK(Rn, Rm) ;\
192 stc sr, Rm ;\
193 or Rn, Rm ;\
    [all...]
  /src/sys/arch/aarch64/aarch64/
disasm.c 799 uint64_t sf, uint64_t Rm, uint64_t option, uint64_t imm3,
811 PRINTF("%s, %s", SREGNAME(sf, Rn), ZREGNAME(r, Rm));
842 uint64_t sf, uint64_t shift, uint64_t Rm, uint64_t imm6,
855 ZREGNAME(sf, Rm));
860 ZREGNAME(sf, Rm));
866 ZREGNAME(sf, Rm));
890 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt,
905 ZREGNAME(r, Rm),
913 ZREGNAME(r, Rm),
922 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt
    [all...]
trap.c 683 int Rn, Rd, Rm, error;
687 Rm = __SHIFTOUT(insn, 0x0000000f);
690 val = tf->tf_reg[Rm];
  /src/external/gpl3/gdb/dist/sim/arm/
thumbemu.c 267 case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
270 ARMword Rm = ntBITS (0, 3);
278 * ainstr |= (Rm);
290 ARMword Rm = ntBITS (0, 3);
296 address = state->Reg[Rn] + state->Reg[Rm] * 2;
302 address = state->Reg[Rn] + state->Reg[Rm];
410 ARMword Rm = ntBITS (0, 3);
420 // TST<c>.W <Rn>,<Rm>{,<shift>}
425 // AND{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
438 * ainstr |= (Rm << 0)
    [all...]
armemu.c 273 ARMword Rm;
340 Rm = BITS (0, 3);
342 if (Rd == 15 || Rn == 15 || Rm == 15)
346 val2 = state->Reg[Rm];
350 case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
374 case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
410 case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
446 case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
470 case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
494 case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. *
    [all...]
iwmmxt.c 983 ARMword Rm = state->Reg [BITS (0, 3)];
1000 b = SUBSTR (Rm, ARMword, 16, 31);
1013 b = SUBSTR (Rm, ARMword, 0, 15);
1032 ARMword Rm;
1049 Rm = state->Reg [BITS (0, 3)];
1051 Rm >>= 16;
1053 Rm &= 0xffff;
1061 if (Rm & (1 << 15))
1062 Rm -= 1 << 16;
1067 Rm *= Rs
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 267 case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
270 ARMword Rm = ntBITS (0, 3);
278 * ainstr |= (Rm);
290 ARMword Rm = ntBITS (0, 3);
296 address = state->Reg[Rn] + state->Reg[Rm] * 2;
302 address = state->Reg[Rn] + state->Reg[Rm];
410 ARMword Rm = ntBITS (0, 3);
420 // TST<c>.W <Rn>,<Rm>{,<shift>}
425 // AND{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
438 * ainstr |= (Rm << 0)
    [all...]
armemu.c 273 ARMword Rm;
340 Rm = BITS (0, 3);
342 if (Rd == 15 || Rn == 15 || Rm == 15)
346 val2 = state->Reg[Rm];
350 case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
374 case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
410 case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
446 case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
470 case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
494 case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. *
    [all...]
iwmmxt.c 983 ARMword Rm = state->Reg [BITS (0, 3)];
1000 b = SUBSTR (Rm, ARMword, 16, 31);
1013 b = SUBSTR (Rm, ARMword, 0, 15);
1032 ARMword Rm;
1049 Rm = state->Reg [BITS (0, 3)];
1051 Rm >>= 16;
1053 Rm &= 0xffff;
1061 if (Rm & (1 << 15))
1062 Rm -= 1 << 16;
1067 Rm *= Rs
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 1474 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1479 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1511 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1516 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1954 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1999 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2032 if (type && Rm == 15
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-arm.c 2409 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5530 <Rm>
5531 <Rm>, <shift>
5731 <Rm>
5732 <Rm>, <shift>
5814 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5815 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5823 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/
18794 int rm; local
19587 unsigned rm local
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-arm.c 2408 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5529 <Rm>
5530 <Rm>, <shift>
5730 <Rm>
5731 <Rm>, <shift>
5813 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5814 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5822 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/
18797 int rm; local
19590 unsigned rm local
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
aarch64-tbl.h 3205 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3233 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3234 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3235 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3236 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3237 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3238 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3927 CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF),
3928 CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF),
3930 CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF)
    [all...]
arm-dis.c 4340 %S print a possibly-shifted Rm
5645 unsigned long rm, rn;
5646 rm = arm_decode_field (given, 0, 3);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
8568 const char *rm = arm_regnames [given & 0xf];
8579 func (stream, dis_style_register, "%s", rm);
8596 func (stream, dis_style_register, "%s", rm);
9077 int rm = ((given >> 0) & 0xf);
9112 if (rm == 0xd
5644 unsigned long rm, rn; local
8567 const char *rm = arm_regnames [given & 0xf]; local
9076 int rm = ((given >> 0) & 0xf); local
9126 int rm = ((given >> 0) & 0xf); local
9214 int rm = ((given >> 0) & 0xf); local
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
aarch64-tbl.h 3015 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3043 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3044 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3045 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3046 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3047 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3048 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3737 CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF),
3738 CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF),
3740 CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF)
    [all...]
arm-dis.c 4433 %S print a possibly-shifted Rm
5741 unsigned long rm, rn;
5742 rm = arm_decode_field (given, 0, 3);
5745 if (rm == 0xf && rn == 0xf)
5748 else if (rn == rm && rn != 0xf)
8761 const char *rm = arm_regnames [given & 0xf];
8772 func (stream, dis_style_register, "%s", rm);
8789 func (stream, dis_style_register, "%s", rm);
9270 int rm = ((given >> 0) & 0xf);
9305 if (rm == 0xd
5740 unsigned long rm, rn; local
8760 const char *rm = arm_regnames [given & 0xf]; local
9269 int rm = ((given >> 0) & 0xf); local
9319 int rm = ((given >> 0) & 0xf); local
9407 int rm = ((given >> 0) & 0xf); local
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
aarch64-tbl.h 3642 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3691 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3692 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3693 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3694 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3695 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3696 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
4382 CMPBR_INSN ("cbgt", 0x74000000, 0x7fe0c000, compbranch, OP3 (Rt, Rm, ADDR_PCREL9), QL_R2NIL, F_SF | F_HAS_ALIAS),
4383 CMPBR_INSN ("cblt", 0x74000000, 0x7fe0c000, compbranch, OP3 (Rm, Rt, ADDR_PCREL9), QL_R2NIL, F_SF | F_ALIAS | F_PSEUDO),
4384 CMPBR_INSN ("cbge", 0x74200000, 0x7fe0c000, compbranch, OP3 (Rt, Rm, ADDR_PCREL9), QL_R2NIL, F_SF | F_HAS_ALIAS)
    [all...]
arm-dis.c 4340 %S print a possibly-shifted Rm
5645 unsigned long rm, rn;
5646 rm = arm_decode_field (given, 0, 3);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
8568 const char *rm = arm_regnames [given & 0xf];
8579 func (stream, dis_style_register, "%s", rm);
8596 func (stream, dis_style_register, "%s", rm);
9077 int rm = ((given >> 0) & 0xf);
9112 if (rm == 0xd
5644 unsigned long rm, rn; local
8567 const char *rm = arm_regnames [given & 0xf]; local
9076 int rm = ((given >> 0) & 0xf); local
9126 int rm = ((given >> 0) & 0xf); local
9214 int rm = ((given >> 0) & 0xf); local
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
aarch64-tbl.h 3443 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3471 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3472 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3473 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3475 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
4162 CMPBR_INSN ("cbgt", 0x74000000, 0x7fe0c000, compbranch, OP3 (Rt, Rm, ADDR_PCREL9), QL_R2NIL, F_SF | F_HAS_ALIAS),
4163 CMPBR_INSN ("cblt", 0x74000000, 0x7fe0c000, compbranch, OP3 (Rm, Rt, ADDR_PCREL9), QL_R2NIL, F_SF | F_ALIAS | F_PSEUDO),
4164 CMPBR_INSN ("cbge", 0x74200000, 0x7fe0c000, compbranch, OP3 (Rt, Rm, ADDR_PCREL9), QL_R2NIL, F_SF | F_HAS_ALIAS)
    [all...]
arm-dis.c 4340 %S print a possibly-shifted Rm
5645 unsigned long rm, rn;
5646 rm = arm_decode_field (given, 0, 3);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
8568 const char *rm = arm_regnames [given & 0xf];
8579 func (stream, dis_style_register, "%s", rm);
8596 func (stream, dis_style_register, "%s", rm);
9077 int rm = ((given >> 0) & 0xf);
9112 if (rm == 0xd
5644 unsigned long rm, rn; local
8567 const char *rm = arm_regnames [given & 0xf]; local
9076 int rm = ((given >> 0) & 0xf); local
9126 int rm = ((given >> 0) & 0xf); local
9214 int rm = ((given >> 0) & 0xf); local
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 982 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1010 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1031 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1586 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1600 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1606 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1612 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1618 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1624 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1630 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 3473 Register Rm = MI.getOperand(3).getReg();
3474 return (Rt == Rm) ? 4 : 3;
3480 Register Rm = MI.getOperand(3).getReg();
3481 if (Rt == Rm)
3510 Register Rm = MI.getOperand(3).getReg();
3511 if (!Rm)
3513 if (Rt == Rm)
3522 Register Rm = MI.getOperand(3).getReg();
3523 return (Rt == Rm) ? 3 : 2;
3541 Register Rm = MI.getOperand(3).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 927 // [Rn, Rm]
928 // {5-3} = Rm
933 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
934 return (Rm << 3) | Rn;
1255 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1268 // {3-0} = Rm
1272 uint32_t Binary = Rm;
1285 // {13} 1 == imm12, 0 == Rm
1287 // {11-0} imm12/Rm
1294 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm1
    [all...]
  /src/external/gpl3/gdb/dist/sim/sh/
interp.c 120 #define Rm saved_state.asregs.regs[m]
1157 dmul_s (uint32_t rm, uint32_t rn)
1159 int64_t res = (int64_t)(int32_t)rm * (int64_t)(int32_t)rn;
1165 dmul_u (uint32_t rm, uint32_t rn)
1167 uint64_t res = (uint64_t)(uint32_t)rm * (uint64_t)(uint32_t)rn;
  /src/external/gpl3/gdb.old/dist/sim/sh/
interp.c 120 #define Rm saved_state.asregs.regs[m]
1157 dmul_s (uint32_t rm, uint32_t rn)
1159 int64_t res = (int64_t)(int32_t)rm * (int64_t)(int32_t)rn;
1165 dmul_u (uint32_t rm, uint32_t rn)
1167 uint64_t res = (uint64_t)(uint32_t)rm * (uint64_t)(uint32_t)rn;

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