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    Searched refs:Rn (Results 1 - 25 of 32) sorted by relevancy

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  /src/sys/arch/aarch64/aarch64/
disasm.c 800 uint64_t Rn, uint64_t Rd,
811 PRINTF("%s, %s", SREGNAME(sf, Rn), ZREGNAME(r, Rm));
813 if ((Rd == 31) || (Rn == 31)) {
843 uint64_t Rn, uint64_t Rd,
851 if ((dzm_op != NULL) && (Rn == 31)) {
859 ZREGNAME(sf, Rn),
865 ZREGNAME(sf, Rn),
890 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt,
904 SREGNAME(1, Rn),
912 SREGNAME(1, Rn),
    [all...]
trap.c 683 int Rn, Rd, Rm, error;
685 Rn = __SHIFTOUT(insn, 0x000f0000);
689 vaddr = tf->tf_reg[Rn] & 0xffffffff;
  /src/external/gpl3/binutils/dist/include/opcode/
tic30.h 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
    [all...]
  /src/external/gpl3/binutils.old/dist/include/opcode/
tic30.h 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
    [all...]
  /src/external/gpl3/gdb.old/dist/include/opcode/
tic30.h 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
    [all...]
  /src/external/gpl3/gdb/dist/include/opcode/
tic30.h 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
    [all...]
  /src/sys/arch/sh3/include/
locore.h 169 #define __EXCEPTION_BLOCK(Rn, Rm) ;\
170 mov #0x10, Rn ;\
171 swap.b Rn, Rn ;\
172 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\
174 or Rm, Rn ;\
175 ldc Rn, sr /* block exceptions */
177 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 267 case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
269 ARMword Rn = tBITS (0, 3);
277 * ainstr |= (Rn << 16);
289 ARMword Rn = tBITS (0, 3);
296 address = state->Reg[Rn] + state->Reg[Rm] * 2;
302 address = state->Reg[Rn] + state->Reg[Rm];
320 ARMword Rn = tBITS (0, 3);
334 if (Rn == 15)
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8
    [all...]
armemu.c 274 ARMword Rn;
339 Rn = BITS (16, 19);
342 if (Rd == 15 || Rn == 15 || Rm == 15)
345 val1 = state->Reg[Rn];
350 case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
374 case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
410 case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
446 case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
470 case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
494 case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. *
    [all...]
iwmmxt.c 672 ARMdword Rn;
682 Rn = state->Reg [BITS (12, 15)];
684 Rn &= 0xfffffffc;
691 Rn &= 0xff;
692 wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
693 | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 1579 // Writeback not allowed if Rn is in the target list.
1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1908 if (writeback && (Rn == 15 || Rn == Rt))
1953 unsigned Rn = fieldFromInstruction(Val, 13, 4)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 890 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
895 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
898 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
981 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1009 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1030 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1076 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1127 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1137 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1195 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder)
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
aarch64-tbl.h 3194 MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \
3233 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3234 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3235 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3237 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3257 CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
3258 CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3259 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
3260 CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3262 CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF)
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-arm.c 2409 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5813 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5814 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5815 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5822 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5823 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/
    [all...]
tc-tic30.c 566 current_op->op_type = Rn;
881 if ((p_insn.operand_type[count][i]->op_type & Rn) && i < 2)
889 if ((p_insn.tm->operand_types[0][0] & (Indirect | Rn))
890 == (Indirect | Rn))
924 p_insn.p_field = 0x00000000; /* Ind * Ind, Rn +/- Rn. */
926 p_insn.p_field = 0x01000000; /* Ind * Rn, Ind +/- Rn. */
928 p_insn.p_field = 0x03000000; /* Ind * Rn, Rn +/- Ind. *
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-arm.c 2408 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5812 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5813 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5814 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5821 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5822 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/
    [all...]
tc-tic30.c 566 current_op->op_type = Rn;
881 if ((p_insn.operand_type[count][i]->op_type & Rn) && i < 2)
889 if ((p_insn.tm->operand_types[0][0] & (Indirect | Rn))
890 == (Indirect | Rn))
924 p_insn.p_field = 0x00000000; /* Ind * Ind, Rn +/- Rn. */
926 p_insn.p_field = 0x01000000; /* Ind * Rn, Ind +/- Rn. */
928 p_insn.p_field = 0x03000000; /* Ind * Rn, Rn +/- Ind. *
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
aarch64-tbl.h 3631 MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \
3691 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3692 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3693 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3695 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3715 CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
3716 CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3717 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
3718 CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3720 CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF)
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
aarch64-tbl.h 3432 MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \
3471 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3472 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3473 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3475 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3495 CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
3496 CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3497 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
3498 CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3500 CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF)
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
aarch64-tbl.h 3432 MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \
3471 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3472 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3473 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3475 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3495 CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
3496 CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3497 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
3498 CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3500 CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 927 // [Rn, Rm]
929 // {2-0} = Rn
932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
934 return (Rm << 3) | Rn;
997 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1063 // {6-3} Rn
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1073 return (Rn << 3) | Qm;
1122 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1254 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
473 assert(isARMLowRegister(Rn));
481 .addReg(Rn, RegState::Define)
482 .addReg(Rn)
ARMBaseInstrInfo.cpp 2520 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
3560 Register Rn = MI.getOperand(2).getReg();
3565 return (Rt == Rn) ? 3 : 2;
3586 Register Rn = MI.getOperand(3).getReg();
3591 return (Rt == Rn) ? 4 : 3;
3596 Register Rn = MI.getOperand(3).getReg();
3597 return (Rt == Rn) ? 4 : 3;
3633 Register Rn = MI.getOperand(2).getReg();
3634 return (Rt == Rn) ? 3 : 2;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4209 unsigned Rn = Inst.getOperand(3).getReg();
4210 if (RI->isSubRegisterEq(Rn, Rt))
4213 if (RI->isSubRegisterEq(Rn, Rt2))
4255 unsigned Rn = Inst.getOperand(3).getReg();
4256 if (RI->isSubRegisterEq(Rn, Rt))
4259 if (RI->isSubRegisterEq(Rn, Rt2))
4287 unsigned Rn = Inst.getOperand(2).getReg();
4288 if (RI->isSubRegisterEq(Rn, Rt))
4306 unsigned Rn = Inst.getOperand(2).getReg();
4307 if (RI->isSubRegisterEq(Rn, Rt)
    [all...]
  /src/sys/arch/m68k/060sp/dist/
isp.s 1889 # accordingly. If Rn is a data register, Rn is also sign extended. If #
1890 # Rn is an address register, it need not be sign extended since the #
1893 # If the instruction is chk2 and the Rn value is out-of-bounds, set #
1940 # sign extend Rn to long, also.
1964 # sign extend Rn to long, also.
1987 # (1) save 'Z' bit from (Rn - lo)
1988 # (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
1993 sub.l %d0, %d2 # (Rn - lo)
1997 cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi)
    [all...]

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