| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 110 // P0 = cmp.eq(Rs,#u2)
122 // Rd = Rs
163 // Rd=Rs ; jump #r9:2
201 MCOperand Rs, Rt;
223 Rs = L.getOperand(1);
229 CompoundInsn->addOperand(Rs);
236 Rs = L.getOperand(1);
242 CompoundInsn->addOperand(Rs);
249 Rs = L.getOperand(1);
255 CompoundInsn->addOperand(Rs);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5);
639 Rs)));
641 Rs)));
650 InsnType Rs = fieldFromInstruction(insn, 21, 5);
653 Rs)));
655 Rs)));
671 // BOVC if rs >= rt
672 // BEQZALC if rs == 0 && rt != 0
673 // BEQC if rs < rt && rs !=
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| xray_mips.cc | 24 PO_ADDIU = 0x24000000, // addiu rt, rs, imm
26 PO_LUI = 0x3C000000, // lui rs, %hi(address)
27 PO_ORI = 0x34000000, // ori rt, rs, %lo(address)
28 PO_JALR = 0x0000F809, // jalr rs
41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
44 return (Opcode | Rs << 21 | Rt << 16 | Imm);
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
|
| xray_mips64.cc | 24 PO_DADDIU = 0x64000000, // daddiu rt, rs, imm
27 PO_ORI = 0x34000000, // ori rt, rs, imm
29 PO_JALR = 0x00000009, // jalr rs
42 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
45 return (Opcode | Rs << 21 | Rt << 16 | Imm);
49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
51 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
|
| /src/external/gpl3/gcc.old/dist/libphobos/src/std/algorithm/ |
| setops.d | 1176 struct SetIntersection(alias less = "a < b", Rs...)
1177 if (Rs.length >= 2 && allSatisfy!(isInputRange, Rs) &&
1178 !is(CommonType!(staticMap!(ElementType, Rs)) == void))
1181 Rs _input;
1183 alias ElementType = CommonType!(staticMap!(.ElementType, Rs));
1190 size_t done = Rs.length;
1191 static if (Rs.length > 1) while (true)
1195 alias next = _input[(i + 1) % Rs.length];
1204 done = Rs.length
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonConstExtenders.cpp | 277 // In memw(Rs+##V), the ##V could be replaced by a register Rt to
278 // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
280 // another instruction memw(Rs+##V+4), it would need a different Rt.
281 // Now, if Rt was initialized as "##V+Rs<<0", both of these
288 // Include shifting the Rs to account for the ur addressing mode:
289 // ##Val + Rs << S
290 // ##Val - Rs
291 Register Rs;
296 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {
[all...] |
| HexagonSplitDouble.cpp | 103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second;
148 if (Rs.find(Reg) != Rs.end())
374 Register Rs = MI->getOperand(1).getReg();
376 return profit(Rs) + profit(Rt);
476 USet &Rs) {
560 Rs.insert(DP.begin(), End);
561 Rs.insert(CmpR1);
562 Rs.insert(CmpR2)
[all...] |
| /src/etc/rc.d/ |
| rtadvd | 34 while getopts c:dDfM:Rs o; do
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| ScalarEvolutionDivision.cpp | 149 SmallVector<const SCEV *, 2> Qs, Rs;
161 Rs.push_back(R);
166 Remainder = Rs[0];
171 Remainder = SE.getAddExpr(Rs);
|
| /src/external/bsd/mdocml/dist/ |
| mdoc.h | 152 struct mdoc_rs Rs;
|
| /src/sys/arch/sh3/include/ |
| locore.h | 209 #define __INTR_MASK_EXCEPTION_UNBLOCK(Rs, Ri, Rb) \
214 stc sr, Rs ;\
216 or Ri, Rs /* SR |= PSL_IMASK */ ;\
217 and Rb, Rs /* SR &= ~PSL_BL */ ;\
218 ldc Rs, sr
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/ |
| MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) {
155 switch (Rs) {
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4);
184 return DecodeSrcAddrMode(Rs, As);
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4);
190 return DecodeSrcAddrMode(Rs, As);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg();
140 Register Reg = Rs == GAReg ? Rt : Rs;
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-tbl.h | 4232 CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4233 CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4238 CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4239 CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4244 CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4245 CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4246 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4247 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4294 _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
4295 _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0)
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-tbl.h | 4746 CORE_INSN ("stxrb", 0x08007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4747 CORE_INSN ("stlxrb", 0x0800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4752 CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4753 CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4758 CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4759 CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4760 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4761 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4782 _LSCP_INSN ("ldap", 0xd9405800, 0xffe0fc00, ldstpair_off, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, F_LDST_LOAD),
4783 _LSCP_INSN ("ldapp", 0xd9407800, 0xffe0fc00, ldstpair_off, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, F_LDST_LOAD)
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-tbl.h | 4526 CORE_INSN ("stxrb", 0x08007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4527 CORE_INSN ("stlxrb", 0x0800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4532 CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4533 CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4538 CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4539 CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4540 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4541 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4588 _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
4589 _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0)
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-tbl.h | 4526 CORE_INSN ("stxrb", 0x08007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4527 CORE_INSN ("stlxrb", 0x0800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4532 CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4533 CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
4538 CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4539 CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
4540 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4541 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4588 _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
4589 _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0)
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/h8300/ |
| andl.s | 59 ;; and.l Rs,Rd
|
| andw.s | 41 ;; and.w Rs,Rd
|
| orl.s | 59 ;; or.l Rs,Rd
|
| orw.s | 41 ;; or.w Rs,Rd
|
| xorl.s | 59 ;; xor.l Rs,Rd
|
| xorw.s | 41 ;; xor.w Rs,Rd
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/h8300/ |
| andl.s | 59 ;; and.l Rs,Rd
|
| andw.s | 41 ;; and.w Rs,Rd
|
