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    Searched refs:RsrcIdx (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.h 81 MachineRegisterInfo &MRI, int RSrcIdx) const;
162 int RsrcIdx) const;
AMDGPURegisterBankInfo.cpp 1293 MachineRegisterInfo &MRI, int RsrcIdx) const {
1298 RsrcIdx += NumDefs + 1;
1310 if (I == RsrcIdx || I == RsrcIdx + 1)
3161 int RsrcIdx) const {
3164 RsrcIdx += MI.getNumExplicitDefs() + 1;
3186 const bool MustBeSGPR = I == RsrcIdx || I == RsrcIdx + 1;
SIInstrInfo.cpp 5544 int RsrcIdx =
5546 if (RsrcIdx != -1) {
5548 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
5549 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
7138 int RSrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
7139 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 590 int RsrcIdx =
592 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;

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