| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 1811 OP4FUNC(op_ldaxp, size, Rt2, Rn, Rt)
1815 ZREGNAME(size, Rt2),
1840 OP5FUNC(op_ldnp, sf, imm7, Rt2, Rn, Rt)
1845 ZREGNAME(sf, Rt2),
1850 ZREGNAME(sf, Rt2),
1856 OP5FUNC(op_ldp_postidx, sf, imm7, Rt2, Rn, Rt)
1860 ZREGNAME(sf, Rt2),
1865 OP5FUNC(op_ldp_preidx, sf, imm7, Rt2, Rn, Rt)
1869 ZREGNAME(sf, Rt2),
1874 OP5FUNC(op_ldp_signed, sf, imm7, Rt2, Rn, Rt
[all...] |
| db_trace.c | 390 uint64_t Rt2 = (insn >> 10) & 0x1f;
397 } else if (Rt2 == 30) {
411 if (func_entry_autodetect && Rt1 == 29 && Rt2 == 30)
420 uint64_t Rt2 = (insn >> 10) & 0x1f;
426 Rt2, imm7);
429 } else if (Rt2 == 30) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1336 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1390 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1399 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1408 Rt == Rt2)
1419 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1483 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1496 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1507 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1518 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1529 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 2006 unsigned Rt2 = Rt + 1;
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2034 if (Rt2 == 15)
2053 if (Rt2 == 15)
2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2063 if (writeback && (Rn == Rt || Rn == Rt2))
5475 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5480 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 4200 // the Rt == Rt2. All of those are undefined behaviour.
4208 unsigned Rt2 = Inst.getOperand(2).getReg();
4213 if (RI->isSubRegisterEq(Rn, Rt2))
4225 unsigned Rt2 = Inst.getOperand(1).getReg();
4226 if (Rt == Rt2)
4227 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4238 unsigned Rt2 = Inst.getOperand(2).getReg();
4239 if (Rt == Rt2)
4240 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4254 unsigned Rt2 = Inst.getOperand(2).getReg()
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 322 ARMword Rt2 = ntBITS (8, 11);
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-tbl.h | 4760 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4761 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4764 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4765 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4786 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4787 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4791 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4792 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4795 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4796 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_SUBCLASS_OTHER)
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-tbl.h | 4540 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4541 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4544 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4545 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4562 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4563 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4567 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4568 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4571 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4572 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_SUBCLASS_OTHER)
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-tbl.h | 4540 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4541 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4544 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4545 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4562 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4563 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4567 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4568 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4571 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4572 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_SUBCLASS_OTHER)
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-tbl.h | 4246 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4247 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
4250 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4251 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
4268 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4269 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4273 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
4274 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
4277 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4278 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_SUBCLASS_OTHER)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 5813 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5817 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
6932 // We have to be careful to not emit an invalid Rt2 here, because the rest of
7416 unsigned Rt2 = MRI->getEncodingValue(Reg2);
7418 // Rt2 must be Rt + 1 and Rt must be even.
7419 if (Rt + 1 != Rt2 || (Rt & 1)) {
7537 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7550 // Rt2 must be Rt + 1.
7551 if (Rt2 != Rt + 1) {
7565 if (Rt2 == Rt
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 6679 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6902 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7957 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
19817 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19823 Rt2 = 3;
19829 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19832 || inst.operands[Rt2].reg == REG_SP,
19835 || inst.operands[Rt2].reg == REG_PC,
19841 inst.instruction |= inst.operands[Rt2].reg << 16;
19899 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 6682 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6905 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7960 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
19820 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19826 Rt2 = 3;
19832 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19835 || inst.operands[Rt2].reg == REG_SP,
19838 || inst.operands[Rt2].reg == REG_PC,
19844 inst.instruction |= inst.operands[Rt2].reg << 16;
19902 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 7351 // the intrinsic has 4 because Rt and Rt2
7364 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1);
7365 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty);
7367 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});
|
