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    Searched refs:SADDSAT (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 320 SADDSAT,
TargetLowering.h 2438 case ISD::SADDSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 2402 { ISD::SADDSAT, MVT::v32i16, 1 },
2403 { ISD::SADDSAT, MVT::v64i8, 1 },
2474 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split
2475 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split
2529 { ISD::SADDSAT, MVT::v16i16, 1 },
2530 { ISD::SADDSAT, MVT::v32i8, 1 },
2584 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2585 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2696 { ISD::SADDSAT, MVT::v8i16, 1 },
2697 { ISD::SADDSAT, MVT::v16i8, 1 }
    [all...]
X86ISelLowering.cpp 960 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
964 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
1358 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1362 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1685 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 452 case ISD::SADDSAT:
849 case ISD::SADDSAT:
SelectionDAGDumper.cpp 315 case ISD::SADDSAT: return "saddsat";
LegalizeIntegerTypes.cpp 167 case ISD::SADDSAT:
808 case ISD::SADDSAT:
835 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
2180 case ISD::SADDSAT:
LegalizeVectorTypes.cpp 128 case ISD::SADDSAT:
1038 case ISD::SADDSAT:
3027 case ISD::SADDSAT:
LegalizeDAG.cpp 1134 case ISD::SADDSAT:
3371 case ISD::SADDSAT:
SelectionDAG.cpp 5068 case ISD::SADDSAT: return C1.sadd_sat(C2);
5568 case ISD::SADDSAT:
5577 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT)
5929 case ISD::SADDSAT:
TargetLowering.cpp 7978 case ISD::SADDSAT:
8345 // If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
8346 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
SelectionDAGBuilder.cpp 6420 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
DAGCombiner.cpp 1611 case ISD::SADDSAT:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 756 setOperationAction(ISD::SADDSAT, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 452 setOperationAction(ISD::SADDSAT, MVT::i16, Legal);
454 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
678 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal);
709 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom);
4549 case ISD::SADDSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 222 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
280 setOperationAction(ISD::SADDSAT, VT, Legal);
1106 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1108 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1112 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
4838 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
9916 case ISD::SADDSAT:
10016 case ISD::SADDSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 161 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 318 setOperationAction(ISD::SADDSAT, VT, Legal);
1039 setOperationAction(ISD::SADDSAT, VT, Legal);
14041 return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true);
14049 return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0),
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 716 setOperationAction(ISD::SADDSAT, VT, Legal);

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