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    Searched refs:SBIC_ASR_DBR (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/acorn32/podulebus/
sbicreg.h 98 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
440 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
448 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
sbic.c 299 if (asr & SBIC_ASR_DBR) {
663 while (asr & SBIC_ASR_DBR) {
671 if (asr & SBIC_ASR_DBR)
1143 while ((asr & SBIC_ASR_DBR) == 0) {
1201 while ((asr & SBIC_ASR_DBR) == 0) {
1424 if (asr & SBIC_ASR_DBR) {
1436 if (asr & SBIC_ASR_DBR) /* Wants us to write */
1727 if (asr & SBIC_ASR_DBR) {
1739 if (asr & SBIC_ASR_DBR) /* Wants us to write */
1836 (SBIC_ASR_DBR | SBIC_ASR_INT))
    [all...]
  /src/sys/arch/amiga/dev/
sbicreg.h 98 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
413 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
421 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
sbic.c 271 if (asr & SBIC_ASR_DBR) {
752 while (asr & SBIC_ASR_DBR) {
759 if (asr & SBIC_ASR_DBR) /* Not the read direction, then */
1205 while ((asr & SBIC_ASR_DBR) == 0) {
1266 while ((asr & SBIC_ASR_DBR) == 0) {
1496 if (asr & SBIC_ASR_DBR) {
1507 if (asr & SBIC_ASR_DBR) /* Wants us to write */
1893 if (asr & SBIC_ASR_DBR) {
1904 if (asr & SBIC_ASR_DBR) /* Wants us to write */
2001 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT)
    [all...]
  /src/sys/arch/mvme68k/dev/
sbicreg.h 98 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
420 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
431 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
sbic.c 231 if (asr & SBIC_ASR_DBR) {
764 while (asr & SBIC_ASR_DBR) {
773 if (asr & SBIC_ASR_DBR)
1204 if (asr & SBIC_ASR_DBR) {
1254 if (asr & SBIC_ASR_DBR) {
1424 if (asr & SBIC_ASR_DBR) {
1441 if (asr & SBIC_ASR_DBR)
1738 if (asr & SBIC_ASR_DBR) {
1752 if (asr & SBIC_ASR_DBR) /* Wants us to write */
  /src/sys/arch/sgimips/stand/common/
iris_scsireg.h 164 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
492 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \
503 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \
iris_scsi.c 509 if ((asr & SBIC_ASR_DBR) != 0) {
583 if ((asr & SBIC_ASR_DBR) != 0) {
655 while ((asr & SBIC_ASR_DBR) != 0) {
662 if ((asr & SBIC_ASR_DBR) != 0)
  /src/sys/dev/ic/
wd33c93reg.h 138 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
496 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \
507 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \
wd33c93.c 505 if (asr & SBIC_ASR_DBR) {
921 while (asr & SBIC_ASR_DBR) {
930 if (asr & SBIC_ASR_DBR) /* Not the read direction */
1190 if (asr & SBIC_ASR_DBR) {
1235 if (asr & SBIC_ASR_DBR) {

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