| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 571 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
577 SCALAR_TO_VECTOR,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
280 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo));
703 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
720 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
761 /// with a scalar_to_vector since the res type is legal if we got here
786 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
817 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
832 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
846 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
861 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res)
[all...] |
| SelectionDAGDumper.cpp | 289 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
|
| LegalizeDAG.cpp | 399 // SCALAR_TO_VECTOR requires that the type of the value being inserted
405 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1783 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1864 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1891 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1946 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1949 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2990 case ISD::SCALAR_TO_VECTOR:
4887 case ISD::SCALAR_TO_VECTOR: {
4893 // e.g. v2i64 = scalar_to_vector x:i6
[all...] |
| LegalizeIntegerTypes.cpp | 109 case ISD::SCALAR_TO_VECTOR:
1495 case ISD::SCALAR_TO_VECTOR:
1740 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
4197 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
4766 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
|
| DAGCombiner.cpp | 1716 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
4876 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4878 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
18526 // (vextract (scalar_to_vector val, 0) -> val
18527 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
18528 // Only 0'th element of SCALAR_TO_VECTOR is defined.
18533 // SCALAR_TO_VECTOR may truncate the inserted element and the
18594 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) {
18653 // scalar_to_vector here as well.
18738 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR &
[all...] |
| SelectionDAG.cpp | 2910 case ISD::SCALAR_TO_VECTOR: {
2911 // We know about scalar_to_vector as much as we know about it source,
4534 // FIXME: Add support for SCALAR_TO_VECTOR as well.
4971 case ISD::SCALAR_TO_VECTOR:
4977 "Illegal SCALAR_TO_VECTOR node!");
4980 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
|
| TargetLowering.cpp | 968 case ISD::SCALAR_TO_VECTOR: {
2431 case ISD::SCALAR_TO_VECTOR: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 988 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1421 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1731 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
2006 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2762 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
3002 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3342 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
4103 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
6736 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7428 // SCALAR_TO_VECTOR - only the first element is defined, and the rest UNDEF
[all...] |
| X86ISelDAGToDAG.cpp | 1126 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
1128 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
|
| X86FastISel.cpp | 2643 // The following SCALAR_TO_VECTOR will be expanded into a VMOVDI2PDIrr.
2644 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 425 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
684 // Fill in the missing undef elements if this was a scalar_to_vector.
685 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
758 case ISD::SCALAR_TO_VECTOR:
3077 case ISD::SCALAR_TO_VECTOR:
|
| SIISelLowering.cpp | 259 case ISD::SCALAR_TO_VECTOR:
288 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
289 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
302 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
303 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32);
316 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
317 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
330 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
331 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
582 case ISD::SCALAR_TO_VECTOR
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 817 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
939 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
942 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
947 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
948 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
949 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
2911 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &
[all...] |
| PPCISelDAGToDAG.cpp | 5515 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 378 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
494 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
495 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
4894 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
5156 // Detect SCALAR_TO_VECTOR conversions.
5157 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
5181 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5353 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5469 case ISD::SCALAR_TO_VECTOR:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 337 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
400 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
446 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
5749 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5751 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
7574 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
7701 // scalar_to_vector for the elements followed by a shuffle (provided the
8355 // Test if V1 is a SCALAR_TO_VECTOR.
8356 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8359 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1646 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 9028 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
9809 // SCALAR_TO_VECTOR, except for when we have a single-element constant vector
9813 "SCALAR_TO_VECTOR node\n");
9814 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
9991 // scalar_to_vector for the elements followed by a shuffle (provided the
10003 // Use SCALAR_TO_VECTOR for lane zero to
10015 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0);
15501 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
15503 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
|
