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    Searched refs:SCL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/dev/i2c/
i2c_bitbang.c 56 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
71 while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) {
87 /* start condition: put SDA H->L edge during SCL=H */
90 SETBITS(SDA | SCL);
92 SETBITS( 0 | SCL);
97 /* leave SCL=L and SDA=L to avoid unexpected start/stop condition */
108 /* stop condition: put SDA L->H edge during SCL=H */
110 /* assume SCL=L, SDA=L here */
112 SETBITS( 0 | SCL);
114 SETBITS(SDA | SCL);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_sw.c 36 #define SCL false
92 if (read_bit_from_ddc(ddc, SCL))
120 write_bit_to_ddc(ddc_handle, SCL, true);
125 write_bit_to_ddc(ddc_handle, SCL, false);
131 * after the SCL pulse we use to send our last data bit.
141 write_bit_to_ddc(ddc_handle, SCL, true);
152 write_bit_to_ddc(ddc_handle, SCL, false);
171 * bit is read while SCL is high
175 write_bit_to_ddc(ddc_handle, SCL, true);
183 write_bit_to_ddc(ddc_handle, SCL, false)
    [all...]
dce_transform.h 78 SRI(SCL_MODE, SCL, id), \
79 SRI(SCL_TAP_CONTROL, SCL, id), \
80 SRI(SCL_CONTROL, SCL, id), \
81 SRI(SCL_BYPASS_CONTROL, SCL, id), \
82 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
83 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
84 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
85 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
86 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
87 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id),
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
ddc_regs.h 173 DDC_I2C_REG_LIST(SCL)\
192 DDC_REG_LIST_DCN2(SCL)\

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