| /src/sys/dev/i2c/ |
| i2c_bitbang.c | 56 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
71 while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) {
87 /* start condition: put SDA H->L edge during SCL=H */
90 SETBITS(SDA | SCL);
92 SETBITS( 0 | SCL);
97 /* leave SCL=L and SDA=L to avoid unexpected start/stop condition */
108 /* stop condition: put SDA L->H edge during SCL=H */
110 /* assume SCL=L, SDA=L here */
112 SETBITS( 0 | SCL);
114 SETBITS(SDA | SCL);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_i2c_sw.c | 36 #define SCL false
92 if (read_bit_from_ddc(ddc, SCL))
120 write_bit_to_ddc(ddc_handle, SCL, true);
125 write_bit_to_ddc(ddc_handle, SCL, false);
131 * after the SCL pulse we use to send our last data bit.
141 write_bit_to_ddc(ddc_handle, SCL, true);
152 write_bit_to_ddc(ddc_handle, SCL, false);
171 * bit is read while SCL is high
175 write_bit_to_ddc(ddc_handle, SCL, true);
183 write_bit_to_ddc(ddc_handle, SCL, false)
[all...] |
| dce_transform.h | 78 SRI(SCL_MODE, SCL, id), \
79 SRI(SCL_TAP_CONTROL, SCL, id), \
80 SRI(SCL_CONTROL, SCL, id), \
81 SRI(SCL_BYPASS_CONTROL, SCL, id), \
82 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
83 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
84 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
85 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
86 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
87 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id),
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| ste-dbx5x0-pinctrl.dtsi | 132 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
139 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
152 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
159 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
172 pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
179 pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
190 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
197 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
210 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
217 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
[all...] |
| tegra124-apalis-eval.dts | 68 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
88 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
95 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
|
| tegra30-apalis-eval.dts | 75 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
97 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
105 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
|
| gr-peach-audiocamerashield.dtsi | 23 /* P1_2 as SCL; P1_3 as SDA */
|
| tegra124-apalis-v1.2-eval.dts | 69 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
91 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
100 * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
|
| tegra30-apalis-v1.1-eval.dts | 76 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
98 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
106 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
|
| imx6q-apalis-eval.dts | 130 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
160 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
|
| imx6q-apalis-ixora-v1.1.dts | 135 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
160 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
|
| imx6q-apalis-ixora.dts | 134 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
164 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
|
| omap4-panda-es.dts | 31 /* PandaboardES has external pullups on SCL & SDA */
|
| omap5-igep0050.dts | 106 <&gpio7 2 0>, /* 194, SCL */
|
| r7s72100-genmai.dts | 59 /* RIIC2: P1_4 as SCL, P1_5 as SDA */
|
| at91-foxg20.dts | 124 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* TWCK (SCL), open drain */
|
| imx6dl-colibri-eval-v3.dts | 130 * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
|
| tegra20-colibri-eval-v3.dts | 123 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
|
| tegra20-colibri-iris.dts | 123 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
|
| tegra30-colibri-eval-v3.dts | 59 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
|
| exynos3250-artik5.dtsi | 257 /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
|
| imx6qdl-kontron-samx6i.dtsi | 155 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
166 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
519 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
526 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
533 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
|
| r8a7790-lager.dts | 285 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
295 scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
301 * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
305 * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
320 * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
|
| ste-href-ab8500.dtsi | 354 /* Modem I2C setup (SCL and SDA pins) */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| ddc_regs.h | 173 DDC_I2C_REG_LIST(SCL)\
192 DDC_REG_LIST_DCN2(SCL)\
|
