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    Searched refs:SCLK (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
microchip,pic32-clock.h 20 #define SCLK 7
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
armada-385-turris-omnia.dts 509 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_renoir_ppt.c 119 CLK_MAP(SCLK, CLOCK_GFXCLK),
561 /* The sclk as gfxclk and has three level about max/min/current */
623 pr_info("Currently sclk only support 3 levels on APU\n");
amdgpu_arcturus_ppt.c 139 CLK_MAP(SCLK, PPCLK_GFXCLK),
amdgpu_navi10_ppt.c 139 CLK_MAP(SCLK, PPCLK_GFXCLK),
904 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",

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