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    Searched refs:SCLK_FREQ_SETTING_STEP_0_PART1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_dpm.c	486 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 493 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 500 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), 507 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
r600d.h	1364 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648

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Indexes created Tue Oct 21 15:09:54 GMT 2025