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Searched refs:SCLK_FREQ_SETTING_STEP_0_PART2 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_dpm.c	`454 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 457 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 465 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 468 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 476 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), 479 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),`
r600d.h	`1373 #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c`

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