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    Searched refs:SCS_DP0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/evbmips/alchemy/
dbau1550.c	152 sysclk &= ~(SCS_MP0(7) | SCS_DP0 | SCS_CP0);
/src/sys/arch/mips/alchemy/include/
aureg.h	330 #define SCS_DP0 (1<<6) /* psc0_intclock divider */

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