| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_sdma_v4_0.c | 38 #include "sdma0/sdma0_4_2_offset.h"
39 #include "sdma0/sdma0_4_2_sh_mask.h"
55 #include "sdma0/sdma0_4_1_default.h"
61 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000)
[all...] |
| amdgpu_psp_v10_0.c | 43 #include "sdma0/sdma0_4_1_offset.h"
294 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
295 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
| amdgpu_psp_v12_0.c | 39 #include "sdma0/sdma0_4_0_offset.h"
398 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
399 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
| amdgpu_amdkfd_arcturus.c | 34 #include "sdma0/sdma0_4_2_2_offset.h"
35 #include "sdma0/sdma0_4_2_2_sh_mask.h"
89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
|
| amdgpu_psp_v3_1.c | 44 #include "sdma0/sdma0_4_0_offset.h"
474 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
475 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
| amdgpu_psp_v11_0.c | 42 #include "sdma0/sdma0_4_0_offset.h"
633 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
634 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
|
| amdgpu_amdkfd_gfx_v10.c | 218 SOC15_REG_OFFSET(SDMA0, 0,
221 * on SDMA1 base address (dw 0x1860) but based on SDMA0
|
| amdgpu_amdkfd_gfx_v9.c | 34 #include "sdma0/sdma0_4_0_offset.h"
35 #include "sdma0/sdma0_4_0_sh_mask.h"
228 SOC15_REG_OFFSET(SDMA0, 0,
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| amdgpu_nv.c | 199 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
|
| amdgpu_sdma_v2_4.c | 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
347 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local in function:sdma_v2_4_gfx_stop
352 if ((adev->mman.buffer_funcs_ring == sdma0) ||
364 sdma0->sched.ready = false;
976 /* sdma0 */
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| amdgpu_soc15.c | 46 #include "sdma0/sdma0_4_0_offset.h"
347 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
|
| amdgpu_sdma_v3_0.c | 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
463 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
521 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local in function:sdma_v3_0_gfx_stop
526 if ((adev->mman.buffer_funcs_ring == sdma0) ||
538 sdma0->sched.ready = false;
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik_sdma.c | 47 * and gfx. There are two DMA engines (SDMA0, SDMA1)
183 ref_and_mask = SDMA0;
464 * Loads the sDMA0/1 ucode.
485 /* sdma0 */
505 /* sdma0 */
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| cikd.h | 862 #define SDMA0 (1 << 10)
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