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    Searched refs:SDMA1 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v4_0.c 40 #include "sdma1/sdma1_4_2_offset.h"
41 #include "sdma1/sdma1_4_2_sh_mask.h"
62 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100)
    [all...]
amdgpu_amdkfd_arcturus.c 36 #include "sdma1/sdma1_4_2_2_offset.h"
37 #include "sdma1/sdma1_4_2_2_sh_mask.h"
93 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
amdgpu_amdkfd_gfx_v10.c 221 * on SDMA1 base address (dw 0x1860) but based on SDMA0
226 SOC15_REG_OFFSET(SDMA1, 0,
amdgpu_amdkfd_gfx_v9.c 36 #include "sdma1/sdma1_4_0_offset.h"
37 #include "sdma1/sdma1_4_0_sh_mask.h"
230 SOC15_REG_OFFSET(SDMA1, 0,
amdgpu_nv.c 200 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
amdgpu_sdma_v2_4.c 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
348 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local
353 (adev->mman.buffer_funcs_ring == sdma1))
365 sdma1->sched.ready = false;
983 /* sdma1 */
amdgpu_soc15.c 47 #include "sdma1/sdma1_4_0_offset.h"
348 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
amdgpu_sdma_v3_0.c 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
465 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
522 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local
527 (adev->mman.buffer_funcs_ring == sdma1))
539 sdma1->sched.ready = false;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik_sdma.c 47 * and gfx. There are two DMA engines (SDMA0, SDMA1)
185 ref_and_mask = SDMA1;
494 /* sdma1 */
512 /* sdma1 */
cikd.h 863 #define SDMA1 (1 << 11)

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