1 /* $NetBSD: sdma5_4_2_2_sh_mask.h,v 1.2 2021/12/18 23:45:23 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma5_4_2_2_SH_MASK_HEADER 24 #define _sdma5_4_2_2_SH_MASK_HEADER 25 26 27 // addressBlock: sdma5_sdma5dec 28 //SDMA5_UCODE_ADDR 29 #define SDMA5_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA5_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA5_UCODE_DATA 32 #define SDMA5_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA5_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA5_VM_CNTL 35 #define SDMA5_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA5_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA5_VM_CTX_LO 38 #define SDMA5_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA5_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA5_VM_CTX_HI 41 #define SDMA5_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA5_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA5_ACTIVE_FCN_ID 44 #define SDMA5_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA5_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA5_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA5_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA5_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA5_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA5_VM_CTX_CNTL 51 #define SDMA5_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA5_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA5_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA5_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA5_VIRT_RESET_REQ 56 #define SDMA5_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA5_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA5_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA5_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA5_VF_ENABLE 61 #define SDMA5_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA5_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA5_CONTEXT_REG_TYPE0 64 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA5_CONTEXT_REG_TYPE1 105 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS__SHIFT 0x8 106 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA5_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS_MASK 0x00000100L 121 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA5_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA5_CONTEXT_REG_TYPE2 136 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA5_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA5_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA5_CONTEXT_REG_TYPE3 159 #define SDMA5_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA5_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA5_PUB_REG_TYPE0 162 #define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR__SHIFT 0x0 163 #define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA__SHIFT 0x1 164 #define SDMA5_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 165 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL__SHIFT 0x4 166 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO__SHIFT 0x5 167 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI__SHIFT 0x6 168 #define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID__SHIFT 0x7 169 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL__SHIFT 0x8 170 #define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ__SHIFT 0x9 171 #define SDMA5_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 172 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0__SHIFT 0xb 173 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1__SHIFT 0xc 174 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2__SHIFT 0xd 175 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3__SHIFT 0xe 176 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0__SHIFT 0xf 177 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1__SHIFT 0x10 178 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2__SHIFT 0x11 179 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3__SHIFT 0x12 180 #define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL__SHIFT 0x13 181 #define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 182 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 183 #define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL__SHIFT 0x1a 184 #define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL__SHIFT 0x1b 185 #define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL__SHIFT 0x1c 186 #define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT 0x1d 187 #define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG__SHIFT 0x1e 188 #define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ__SHIFT 0x1f 189 #define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR_MASK 0x00000001L 190 #define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA_MASK 0x00000002L 191 #define SDMA5_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL_MASK 0x00000010L 193 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO_MASK 0x00000020L 194 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI_MASK 0x00000040L 195 #define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID_MASK 0x00000080L 196 #define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL_MASK 0x00000100L 197 #define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ_MASK 0x00000200L 198 #define SDMA5_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0_MASK 0x00008000L 204 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1_MASK 0x00010000L 205 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2_MASK 0x00020000L 206 #define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3_MASK 0x00040000L 207 #define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL_MASK 0x00080000L 208 #define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L 209 #define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 #define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL_MASK 0x04000000L 211 #define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL_MASK 0x08000000L 212 #define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL_MASK 0x10000000L 213 #define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS_MASK 0x20000000L 214 #define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_MASK 0x40000000L 215 #define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 //SDMA5_PUB_REG_TYPE1 217 #define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI__SHIFT 0x0 218 #define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 #define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH__SHIFT 0x2 220 #define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH__SHIFT 0x3 221 #define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM__SHIFT 0x4 222 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG__SHIFT 0x5 223 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG__SHIFT 0x6 224 #define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL__SHIFT 0x7 225 #define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG__SHIFT 0x8 226 #define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM__SHIFT 0x9 227 #define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL__SHIFT 0xa 228 #define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE__SHIFT 0xb 229 #define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM__SHIFT 0xc 230 #define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM__SHIFT 0xd 231 #define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG__SHIFT 0x12 236 #define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD__SHIFT 0x13 237 #define SDMA5_PUB_REG_TYPE1__SDMA5_ID__SHIFT 0x14 238 #define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION__SHIFT 0x15 239 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER__SHIFT 0x16 240 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR__SHIFT 0x17 241 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG__SHIFT 0x18 242 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL__SHIFT 0x19 243 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO__SHIFT 0x1a 244 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI__SHIFT 0x1b 245 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL__SHIFT 0x1c 246 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT 0x1d 247 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS__SHIFT 0x1e 248 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS__SHIFT 0x1f 249 #define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 #define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 #define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_MASK 0x00000004L 252 #define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH_MASK 0x00000008L 253 #define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM_MASK 0x00000010L 254 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG_MASK 0x00000020L 255 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG_MASK 0x00000040L 256 #define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL_MASK 0x00000080L 257 #define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG_MASK 0x00000100L 258 #define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM_MASK 0x00000200L 259 #define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL_MASK 0x00000400L 260 #define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE_MASK 0x00000800L 261 #define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM_MASK 0x00001000L 262 #define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM_MASK 0x00002000L 263 #define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 #define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG_MASK 0x00040000L 268 #define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD_MASK 0x00080000L 269 #define SDMA5_PUB_REG_TYPE1__SDMA5_ID_MASK 0x00100000L 270 #define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION_MASK 0x00200000L 271 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_MASK 0x00400000L 272 #define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 #define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG_MASK 0x01000000L 274 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL_MASK 0x02000000L 275 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO_MASK 0x04000000L 276 #define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI_MASK 0x08000000L 277 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL_MASK 0x10000000L 278 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK_MASK 0x20000000L 279 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS_MASK 0x40000000L 280 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS_MASK 0x80000000L 281 //SDMA5_PUB_REG_TYPE2 282 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0__SHIFT 0x0 283 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1__SHIFT 0x1 284 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2__SHIFT 0x2 285 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0__SHIFT 0x3 286 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1__SHIFT 0x4 287 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0__SHIFT 0x5 288 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1__SHIFT 0x6 289 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT__SHIFT 0x7 290 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE__SHIFT 0x8 291 #define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE__SHIFT 0x9 292 #define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT__SHIFT 0xa 293 #define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2__SHIFT 0xb 294 #define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG__SHIFT 0xc 295 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO__SHIFT 0xd 296 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI__SHIFT 0xe 297 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM__SHIFT 0xf 298 #define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG__SHIFT 0x10 299 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0__SHIFT 0x11 300 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1__SHIFT 0x12 301 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2__SHIFT 0x13 302 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3__SHIFT 0x14 303 #define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER__SHIFT 0x15 304 #define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE__SHIFT 0x16 305 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL__SHIFT 0x17 306 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT__SHIFT 0x18 307 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT__SHIFT 0x19 308 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 309 #define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL__SHIFT 0x1b 310 #define SDMA5_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c 311 #define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 312 #define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL__SHIFT 0x1e 313 #define SDMA5_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 314 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0_MASK 0x00000001L 315 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1_MASK 0x00000002L 316 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2_MASK 0x00000004L 317 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0_MASK 0x00000008L 318 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1_MASK 0x00000010L 319 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0_MASK 0x00000020L 320 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1_MASK 0x00000040L 321 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT_MASK 0x00000080L 322 #define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE_MASK 0x00000100L 323 #define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE_MASK 0x00000200L 324 #define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT_MASK 0x00000400L 325 #define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2_MASK 0x00000800L 326 #define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG_MASK 0x00001000L 327 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO_MASK 0x00002000L 328 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI_MASK 0x00004000L 329 #define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM_MASK 0x00008000L 330 #define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG_MASK 0x00010000L 331 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0_MASK 0x00020000L 332 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1_MASK 0x00040000L 333 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2_MASK 0x00080000L 334 #define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3_MASK 0x00100000L 335 #define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER_MASK 0x00200000L 336 #define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE_MASK 0x00400000L 337 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL_MASK 0x00800000L 338 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT_MASK 0x01000000L 339 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT_MASK 0x02000000L 340 #define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 341 #define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL_MASK 0x08000000L 342 #define SDMA5_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L 343 #define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 344 #define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL_MASK 0x40000000L 345 #define SDMA5_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 346 //SDMA5_PUB_REG_TYPE3 347 #define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA__SHIFT 0x0 348 #define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX__SHIFT 0x1 349 #define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 350 #define SDMA5_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 351 #define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA_MASK 0x00000001L 352 #define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 353 #define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 354 #define SDMA5_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L 355 //SDMA5_MMHUB_CNTL 356 #define SDMA5_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 357 #define SDMA5_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 358 //SDMA5_CONTEXT_GROUP_BOUNDARY 359 #define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 360 #define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 361 //SDMA5_POWER_CNTL 362 #define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 363 #define SDMA5_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 364 #define SDMA5_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 365 #define SDMA5_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 366 #define SDMA5_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 367 #define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 368 #define SDMA5_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 369 #define SDMA5_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 370 #define SDMA5_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 371 #define SDMA5_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 372 //SDMA5_CLK_CTRL 373 #define SDMA5_CLK_CTRL__ON_DELAY__SHIFT 0x0 374 #define SDMA5_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 375 #define SDMA5_CLK_CTRL__RESERVED__SHIFT 0xc 376 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 377 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 378 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 379 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 380 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 381 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 382 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 383 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 384 #define SDMA5_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 385 #define SDMA5_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 386 #define SDMA5_CLK_CTRL__RESERVED_MASK 0x00FFF000L 387 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 388 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 389 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 390 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 391 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 392 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 393 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 394 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 395 //SDMA5_CNTL 396 #define SDMA5_CNTL__TRAP_ENABLE__SHIFT 0x0 397 #define SDMA5_CNTL__UTC_L1_ENABLE__SHIFT 0x1 398 #define SDMA5_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 399 #define SDMA5_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 400 #define SDMA5_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 401 #define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 402 #define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 403 #define SDMA5_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 404 #define SDMA5_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 405 #define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 406 #define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 407 #define SDMA5_CNTL__TRAP_ENABLE_MASK 0x00000001L 408 #define SDMA5_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 409 #define SDMA5_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 410 #define SDMA5_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 411 #define SDMA5_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 412 #define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 413 #define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 414 #define SDMA5_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 415 #define SDMA5_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 416 #define SDMA5_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 417 #define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 418 //SDMA5_CHICKEN_BITS 419 #define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 420 #define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 421 #define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 422 #define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 423 #define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 424 #define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 425 #define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 426 #define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 427 #define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 428 #define SDMA5_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 429 #define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 430 #define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 431 #define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 432 #define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 433 #define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 434 #define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 435 #define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 436 #define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 437 #define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 438 #define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 439 #define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 440 #define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 441 #define SDMA5_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 442 #define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 443 #define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 444 #define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 445 //SDMA5_GB_ADDR_CONFIG 446 #define SDMA5_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 447 #define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 448 #define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 449 #define SDMA5_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 450 #define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 451 #define SDMA5_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 452 #define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 453 #define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 454 #define SDMA5_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 455 #define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 456 //SDMA5_GB_ADDR_CONFIG_READ 457 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 458 #define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 459 #define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 460 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 461 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 462 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 463 #define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 464 #define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 465 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 466 #define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 467 //SDMA5_RB_RPTR_FETCH_HI 468 #define SDMA5_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 469 #define SDMA5_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 470 //SDMA5_SEM_WAIT_FAIL_TIMER_CNTL 471 #define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 472 #define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 473 //SDMA5_RB_RPTR_FETCH 474 #define SDMA5_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 475 #define SDMA5_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 476 //SDMA5_IB_OFFSET_FETCH 477 #define SDMA5_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 478 #define SDMA5_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 479 //SDMA5_PROGRAM 480 #define SDMA5_PROGRAM__STREAM__SHIFT 0x0 481 #define SDMA5_PROGRAM__STREAM_MASK 0xFFFFFFFFL 482 //SDMA5_STATUS_REG 483 #define SDMA5_STATUS_REG__IDLE__SHIFT 0x0 484 #define SDMA5_STATUS_REG__REG_IDLE__SHIFT 0x1 485 #define SDMA5_STATUS_REG__RB_EMPTY__SHIFT 0x2 486 #define SDMA5_STATUS_REG__RB_FULL__SHIFT 0x3 487 #define SDMA5_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 488 #define SDMA5_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 489 #define SDMA5_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 490 #define SDMA5_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 491 #define SDMA5_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 492 #define SDMA5_STATUS_REG__INSIDE_IB__SHIFT 0x9 493 #define SDMA5_STATUS_REG__EX_IDLE__SHIFT 0xa 494 #define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 495 #define SDMA5_STATUS_REG__PACKET_READY__SHIFT 0xc 496 #define SDMA5_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 497 #define SDMA5_STATUS_REG__SRBM_IDLE__SHIFT 0xe 498 #define SDMA5_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 499 #define SDMA5_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 500 #define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 501 #define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 502 #define SDMA5_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 503 #define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 504 #define SDMA5_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 505 #define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 506 #define SDMA5_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 507 #define SDMA5_STATUS_REG__SEM_IDLE__SHIFT 0x1a 508 #define SDMA5_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 509 #define SDMA5_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 510 #define SDMA5_STATUS_REG__INT_IDLE__SHIFT 0x1e 511 #define SDMA5_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 512 #define SDMA5_STATUS_REG__IDLE_MASK 0x00000001L 513 #define SDMA5_STATUS_REG__REG_IDLE_MASK 0x00000002L 514 #define SDMA5_STATUS_REG__RB_EMPTY_MASK 0x00000004L 515 #define SDMA5_STATUS_REG__RB_FULL_MASK 0x00000008L 516 #define SDMA5_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 517 #define SDMA5_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 518 #define SDMA5_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 519 #define SDMA5_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 520 #define SDMA5_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 521 #define SDMA5_STATUS_REG__INSIDE_IB_MASK 0x00000200L 522 #define SDMA5_STATUS_REG__EX_IDLE_MASK 0x00000400L 523 #define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 524 #define SDMA5_STATUS_REG__PACKET_READY_MASK 0x00001000L 525 #define SDMA5_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 526 #define SDMA5_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 527 #define SDMA5_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 528 #define SDMA5_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 529 #define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 530 #define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 531 #define SDMA5_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 532 #define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 533 #define SDMA5_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 534 #define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 535 #define SDMA5_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 536 #define SDMA5_STATUS_REG__SEM_IDLE_MASK 0x04000000L 537 #define SDMA5_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 538 #define SDMA5_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 539 #define SDMA5_STATUS_REG__INT_IDLE_MASK 0x40000000L 540 #define SDMA5_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 541 //SDMA5_STATUS1_REG 542 #define SDMA5_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 543 #define SDMA5_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 544 #define SDMA5_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 545 #define SDMA5_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 546 #define SDMA5_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 547 #define SDMA5_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 548 #define SDMA5_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 549 #define SDMA5_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 550 #define SDMA5_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 551 #define SDMA5_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 552 #define SDMA5_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 553 #define SDMA5_STATUS1_REG__EX_START__SHIFT 0xf 554 #define SDMA5_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 555 #define SDMA5_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 556 #define SDMA5_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 557 #define SDMA5_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 558 #define SDMA5_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 559 #define SDMA5_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 560 #define SDMA5_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 561 #define SDMA5_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 562 #define SDMA5_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 563 #define SDMA5_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 564 #define SDMA5_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 565 #define SDMA5_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 566 #define SDMA5_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 567 #define SDMA5_STATUS1_REG__EX_START_MASK 0x00008000L 568 #define SDMA5_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 569 #define SDMA5_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 570 //SDMA5_RD_BURST_CNTL 571 #define SDMA5_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 572 #define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 573 #define SDMA5_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 574 #define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 575 //SDMA5_HBM_PAGE_CONFIG 576 #define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 577 #define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 578 //SDMA5_UCODE_CHECKSUM 579 #define SDMA5_UCODE_CHECKSUM__DATA__SHIFT 0x0 580 #define SDMA5_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 581 //SDMA5_F32_CNTL 582 #define SDMA5_F32_CNTL__HALT__SHIFT 0x0 583 #define SDMA5_F32_CNTL__STEP__SHIFT 0x1 584 #define SDMA5_F32_CNTL__HALT_MASK 0x00000001L 585 #define SDMA5_F32_CNTL__STEP_MASK 0x00000002L 586 //SDMA5_FREEZE 587 #define SDMA5_FREEZE__PREEMPT__SHIFT 0x0 588 #define SDMA5_FREEZE__FREEZE__SHIFT 0x4 589 #define SDMA5_FREEZE__FROZEN__SHIFT 0x5 590 #define SDMA5_FREEZE__F32_FREEZE__SHIFT 0x6 591 #define SDMA5_FREEZE__PREEMPT_MASK 0x00000001L 592 #define SDMA5_FREEZE__FREEZE_MASK 0x00000010L 593 #define SDMA5_FREEZE__FROZEN_MASK 0x00000020L 594 #define SDMA5_FREEZE__F32_FREEZE_MASK 0x00000040L 595 //SDMA5_PHASE0_QUANTUM 596 #define SDMA5_PHASE0_QUANTUM__UNIT__SHIFT 0x0 597 #define SDMA5_PHASE0_QUANTUM__VALUE__SHIFT 0x8 598 #define SDMA5_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 599 #define SDMA5_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 600 #define SDMA5_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 601 #define SDMA5_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 602 //SDMA5_PHASE1_QUANTUM 603 #define SDMA5_PHASE1_QUANTUM__UNIT__SHIFT 0x0 604 #define SDMA5_PHASE1_QUANTUM__VALUE__SHIFT 0x8 605 #define SDMA5_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 606 #define SDMA5_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 607 #define SDMA5_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 608 #define SDMA5_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 609 //SDMA5_EDC_CONFIG 610 #define SDMA5_EDC_CONFIG__DIS_EDC__SHIFT 0x1 611 #define SDMA5_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 612 #define SDMA5_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 613 #define SDMA5_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 614 //SDMA5_BA_THRESHOLD 615 #define SDMA5_BA_THRESHOLD__READ_THRES__SHIFT 0x0 616 #define SDMA5_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 617 #define SDMA5_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 618 #define SDMA5_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 619 //SDMA5_ID 620 #define SDMA5_ID__DEVICE_ID__SHIFT 0x0 621 #define SDMA5_ID__DEVICE_ID_MASK 0x000000FFL 622 //SDMA5_VERSION 623 #define SDMA5_VERSION__MINVER__SHIFT 0x0 624 #define SDMA5_VERSION__MAJVER__SHIFT 0x8 625 #define SDMA5_VERSION__REV__SHIFT 0x10 626 #define SDMA5_VERSION__MINVER_MASK 0x0000007FL 627 #define SDMA5_VERSION__MAJVER_MASK 0x00007F00L 628 #define SDMA5_VERSION__REV_MASK 0x003F0000L 629 //SDMA5_EDC_COUNTER 630 #define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 631 #define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 632 #define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 633 #define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 634 #define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 635 #define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 636 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 637 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 638 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 639 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 640 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 641 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 642 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 643 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 644 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 645 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 646 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 647 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 648 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 649 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 650 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 651 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 652 #define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 653 #define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 654 #define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 655 #define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 656 #define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 657 #define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 658 #define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 659 #define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 660 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 661 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 662 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 663 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 664 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 665 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 666 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 667 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 668 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 669 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 670 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 671 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 672 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 673 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 674 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 675 #define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 676 #define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 677 #define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 678 //SDMA5_EDC_COUNTER_CLEAR 679 #define SDMA5_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 680 #define SDMA5_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 681 //SDMA5_STATUS2_REG 682 #define SDMA5_STATUS2_REG__ID__SHIFT 0x0 683 #define SDMA5_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 684 #define SDMA5_STATUS2_REG__CMD_OP__SHIFT 0x10 685 #define SDMA5_STATUS2_REG__ID_MASK 0x00000007L 686 #define SDMA5_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 687 #define SDMA5_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 688 //SDMA5_ATOMIC_CNTL 689 #define SDMA5_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 690 #define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 691 #define SDMA5_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 692 #define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 693 //SDMA5_ATOMIC_PREOP_LO 694 #define SDMA5_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 695 #define SDMA5_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 696 //SDMA5_ATOMIC_PREOP_HI 697 #define SDMA5_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 698 #define SDMA5_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 699 //SDMA5_UTCL1_CNTL 700 #define SDMA5_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 701 #define SDMA5_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 702 #define SDMA5_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 703 #define SDMA5_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 704 #define SDMA5_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 705 #define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 706 #define SDMA5_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 707 #define SDMA5_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 708 #define SDMA5_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 709 #define SDMA5_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 710 #define SDMA5_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 711 #define SDMA5_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 712 //SDMA5_UTCL1_WATERMK 713 #define SDMA5_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 714 #define SDMA5_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 715 #define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 716 #define SDMA5_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 717 #define SDMA5_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 718 #define SDMA5_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 719 #define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 720 #define SDMA5_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 721 //SDMA5_UTCL1_RD_STATUS 722 #define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 723 #define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 724 #define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 725 #define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 726 #define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 727 #define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 728 #define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 729 #define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 730 #define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 731 #define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 732 #define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 733 #define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 734 #define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 735 #define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 736 #define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 737 #define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 738 #define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 739 #define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 740 #define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 741 #define SDMA5_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 742 #define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 743 #define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 744 #define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 745 #define SDMA5_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 746 #define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 747 #define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 748 #define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 749 #define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 750 #define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 751 #define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 752 #define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 753 #define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 754 #define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 755 #define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 756 #define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 757 #define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 758 #define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 759 #define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 760 #define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 761 #define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 762 #define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 763 #define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 764 #define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 765 #define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 766 #define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 767 #define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 768 #define SDMA5_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 769 #define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 770 #define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 771 #define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 772 #define SDMA5_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 773 #define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 774 #define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 775 #define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 776 //SDMA5_UTCL1_WR_STATUS 777 #define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 778 #define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 779 #define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 780 #define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 781 #define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 782 #define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 783 #define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 784 #define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 785 #define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 786 #define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 787 #define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 788 #define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 789 #define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 790 #define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 791 #define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 792 #define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 793 #define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 794 #define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 795 #define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 796 #define SDMA5_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 797 #define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 798 #define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 799 #define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 800 #define SDMA5_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 801 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 802 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 803 #define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 804 #define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 805 #define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 806 #define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 807 #define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 808 #define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 809 #define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 810 #define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 811 #define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 812 #define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 813 #define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 814 #define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 815 #define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 816 #define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 817 #define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 818 #define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 819 #define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 820 #define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 821 #define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 822 #define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 823 #define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 824 #define SDMA5_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 825 #define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 826 #define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 827 #define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 828 #define SDMA5_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 829 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 830 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 831 #define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 832 #define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 833 //SDMA5_UTCL1_INV0 834 #define SDMA5_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 835 #define SDMA5_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 836 #define SDMA5_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 837 #define SDMA5_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 838 #define SDMA5_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 839 #define SDMA5_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 840 #define SDMA5_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 841 #define SDMA5_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 842 #define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 843 #define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 844 #define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 845 #define SDMA5_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 846 #define SDMA5_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 847 #define SDMA5_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 848 #define SDMA5_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 849 #define SDMA5_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 850 #define SDMA5_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 851 #define SDMA5_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 852 #define SDMA5_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 853 #define SDMA5_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 854 #define SDMA5_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 855 #define SDMA5_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 856 #define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 857 #define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 858 #define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 859 #define SDMA5_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 860 #define SDMA5_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 861 #define SDMA5_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 862 //SDMA5_UTCL1_INV1 863 #define SDMA5_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 864 #define SDMA5_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 865 //SDMA5_UTCL1_INV2 866 #define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 867 #define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 868 //SDMA5_UTCL1_RD_XNACK0 869 #define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 870 #define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 871 //SDMA5_UTCL1_RD_XNACK1 872 #define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 873 #define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 874 #define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 875 #define SDMA5_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 876 #define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 877 #define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 878 #define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 879 #define SDMA5_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 880 //SDMA5_UTCL1_WR_XNACK0 881 #define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 882 #define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 883 //SDMA5_UTCL1_WR_XNACK1 884 #define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 885 #define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 886 #define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 887 #define SDMA5_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 888 #define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 889 #define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 890 #define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 891 #define SDMA5_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 892 //SDMA5_UTCL1_TIMEOUT 893 #define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 894 #define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 895 #define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 896 #define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 897 //SDMA5_UTCL1_PAGE 898 #define SDMA5_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 899 #define SDMA5_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 900 #define SDMA5_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 901 #define SDMA5_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 902 #define SDMA5_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 903 #define SDMA5_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 904 #define SDMA5_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 905 #define SDMA5_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 906 //SDMA5_POWER_CNTL_IDLE 907 #define SDMA5_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 908 #define SDMA5_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 909 #define SDMA5_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 910 #define SDMA5_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 911 #define SDMA5_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 912 #define SDMA5_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 913 //SDMA5_RELAX_ORDERING_LUT 914 #define SDMA5_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 915 #define SDMA5_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 916 #define SDMA5_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 917 #define SDMA5_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 918 #define SDMA5_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 919 #define SDMA5_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 920 #define SDMA5_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 921 #define SDMA5_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 922 #define SDMA5_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 923 #define SDMA5_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 924 #define SDMA5_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 925 #define SDMA5_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 926 #define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 927 #define SDMA5_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 928 #define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 929 #define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 930 #define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 931 #define SDMA5_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 932 #define SDMA5_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 933 #define SDMA5_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 934 #define SDMA5_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 935 #define SDMA5_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 936 #define SDMA5_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 937 #define SDMA5_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 938 #define SDMA5_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 939 #define SDMA5_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 940 #define SDMA5_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 941 #define SDMA5_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 942 #define SDMA5_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 943 #define SDMA5_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 944 #define SDMA5_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 945 #define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 946 #define SDMA5_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 947 #define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 948 #define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 949 #define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 950 #define SDMA5_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 951 #define SDMA5_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 952 //SDMA5_CHICKEN_BITS_2 953 #define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 954 #define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 955 //SDMA5_STATUS3_REG 956 #define SDMA5_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 957 #define SDMA5_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 958 #define SDMA5_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 959 #define SDMA5_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 960 #define SDMA5_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 961 #define SDMA5_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 962 #define SDMA5_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 963 #define SDMA5_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 964 #define SDMA5_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 965 #define SDMA5_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 966 //SDMA5_PHYSICAL_ADDR_LO 967 #define SDMA5_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 968 #define SDMA5_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 969 #define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 970 #define SDMA5_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 971 #define SDMA5_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 972 #define SDMA5_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 973 #define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 974 #define SDMA5_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 975 //SDMA5_PHYSICAL_ADDR_HI 976 #define SDMA5_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 977 #define SDMA5_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 978 //SDMA5_PHASE2_QUANTUM 979 #define SDMA5_PHASE2_QUANTUM__UNIT__SHIFT 0x0 980 #define SDMA5_PHASE2_QUANTUM__VALUE__SHIFT 0x8 981 #define SDMA5_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 982 #define SDMA5_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 983 #define SDMA5_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 984 #define SDMA5_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 985 //SDMA5_ERROR_LOG 986 #define SDMA5_ERROR_LOG__OVERRIDE__SHIFT 0x0 987 #define SDMA5_ERROR_LOG__STATUS__SHIFT 0x10 988 #define SDMA5_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 989 #define SDMA5_ERROR_LOG__STATUS_MASK 0xFFFF0000L 990 //SDMA5_PUB_DUMMY_REG0 991 #define SDMA5_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 992 #define SDMA5_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 993 //SDMA5_PUB_DUMMY_REG1 994 #define SDMA5_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 995 #define SDMA5_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 996 //SDMA5_PUB_DUMMY_REG2 997 #define SDMA5_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 998 #define SDMA5_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 999 //SDMA5_PUB_DUMMY_REG3 1000 #define SDMA5_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1001 #define SDMA5_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1002 //SDMA5_F32_COUNTER 1003 #define SDMA5_F32_COUNTER__VALUE__SHIFT 0x0 1004 #define SDMA5_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1005 //SDMA5_UNBREAKABLE 1006 #define SDMA5_UNBREAKABLE__VALUE__SHIFT 0x0 1007 #define SDMA5_UNBREAKABLE__VALUE_MASK 0x00000001L 1008 //SDMA5_PERFMON_CNTL 1009 #define SDMA5_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1010 #define SDMA5_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1011 #define SDMA5_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1012 #define SDMA5_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1013 #define SDMA5_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1014 #define SDMA5_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1015 #define SDMA5_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1016 #define SDMA5_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1017 #define SDMA5_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1018 #define SDMA5_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1019 #define SDMA5_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1020 #define SDMA5_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1021 //SDMA5_PERFCOUNTER0_RESULT 1022 #define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1023 #define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1024 //SDMA5_PERFCOUNTER1_RESULT 1025 #define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1026 #define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1027 //SDMA5_PERFCOUNTER_TAG_DELAY_RANGE 1028 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1029 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1030 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1031 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1032 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1033 #define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1034 //SDMA5_CRD_CNTL 1035 #define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1036 #define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1037 #define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1038 #define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1039 //SDMA5_GPU_IOV_VIOLATION_LOG 1040 #define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1041 #define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1042 #define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1043 #define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 1044 #define SDMA5_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 1045 #define SDMA5_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 1046 #define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1047 #define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1048 #define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 1049 #define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 1050 #define SDMA5_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 1051 #define SDMA5_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 1052 //SDMA5_ULV_CNTL 1053 #define SDMA5_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1054 #define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1055 #define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1056 #define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1057 #define SDMA5_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1058 #define SDMA5_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1059 #define SDMA5_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1060 #define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1061 #define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1062 #define SDMA5_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1063 #define SDMA5_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1064 #define SDMA5_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1065 //SDMA5_EA_DBIT_ADDR_DATA 1066 #define SDMA5_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1067 #define SDMA5_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1068 //SDMA5_EA_DBIT_ADDR_INDEX 1069 #define SDMA5_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1070 #define SDMA5_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1071 //SDMA5_GPU_IOV_VIOLATION_LOG2 1072 #define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 1073 #define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL 1074 //SDMA5_GFX_RB_CNTL 1075 #define SDMA5_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1076 #define SDMA5_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1077 #define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1078 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1079 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1080 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1081 #define SDMA5_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1082 #define SDMA5_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1083 #define SDMA5_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1084 #define SDMA5_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1085 #define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1086 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1087 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1088 #define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1089 #define SDMA5_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1090 #define SDMA5_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1091 //SDMA5_GFX_RB_BASE 1092 #define SDMA5_GFX_RB_BASE__ADDR__SHIFT 0x0 1093 #define SDMA5_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1094 //SDMA5_GFX_RB_BASE_HI 1095 #define SDMA5_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1096 #define SDMA5_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1097 //SDMA5_GFX_RB_RPTR 1098 #define SDMA5_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1099 #define SDMA5_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1100 //SDMA5_GFX_RB_RPTR_HI 1101 #define SDMA5_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1102 #define SDMA5_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1103 //SDMA5_GFX_RB_WPTR 1104 #define SDMA5_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1105 #define SDMA5_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1106 //SDMA5_GFX_RB_WPTR_HI 1107 #define SDMA5_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1108 #define SDMA5_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1109 //SDMA5_GFX_RB_WPTR_POLL_CNTL 1110 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1111 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1112 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1113 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1114 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1115 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1116 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1117 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1118 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1119 #define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1120 //SDMA5_GFX_RB_RPTR_ADDR_HI 1121 #define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1122 #define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1123 //SDMA5_GFX_RB_RPTR_ADDR_LO 1124 #define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1125 #define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1126 #define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1127 #define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1128 //SDMA5_GFX_IB_CNTL 1129 #define SDMA5_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1130 #define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1131 #define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1132 #define SDMA5_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1133 #define SDMA5_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1134 #define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1135 #define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1136 #define SDMA5_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1137 //SDMA5_GFX_IB_RPTR 1138 #define SDMA5_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1139 #define SDMA5_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1140 //SDMA5_GFX_IB_OFFSET 1141 #define SDMA5_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1142 #define SDMA5_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1143 //SDMA5_GFX_IB_BASE_LO 1144 #define SDMA5_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1145 #define SDMA5_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1146 //SDMA5_GFX_IB_BASE_HI 1147 #define SDMA5_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1148 #define SDMA5_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1149 //SDMA5_GFX_IB_SIZE 1150 #define SDMA5_GFX_IB_SIZE__SIZE__SHIFT 0x0 1151 #define SDMA5_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1152 //SDMA5_GFX_SKIP_CNTL 1153 #define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1154 #define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1155 //SDMA5_GFX_CONTEXT_STATUS 1156 #define SDMA5_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1157 #define SDMA5_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1158 #define SDMA5_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1159 #define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1160 #define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1161 #define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1162 #define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1163 #define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1164 #define SDMA5_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1165 #define SDMA5_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1166 #define SDMA5_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1167 #define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1168 #define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1169 #define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1170 #define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1171 #define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1172 //SDMA5_GFX_DOORBELL 1173 #define SDMA5_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1174 #define SDMA5_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1175 #define SDMA5_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1176 #define SDMA5_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1177 //SDMA5_GFX_CONTEXT_CNTL 1178 #define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1179 #define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1180 //SDMA5_GFX_STATUS 1181 #define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1182 #define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1183 #define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1184 #define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1185 //SDMA5_GFX_DOORBELL_LOG 1186 #define SDMA5_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1187 #define SDMA5_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1188 #define SDMA5_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1189 #define SDMA5_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1190 //SDMA5_GFX_WATERMARK 1191 #define SDMA5_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1192 #define SDMA5_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1193 #define SDMA5_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1194 #define SDMA5_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1195 //SDMA5_GFX_DOORBELL_OFFSET 1196 #define SDMA5_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1197 #define SDMA5_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1198 //SDMA5_GFX_CSA_ADDR_LO 1199 #define SDMA5_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1200 #define SDMA5_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1201 //SDMA5_GFX_CSA_ADDR_HI 1202 #define SDMA5_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1203 #define SDMA5_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1204 //SDMA5_GFX_IB_SUB_REMAIN 1205 #define SDMA5_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1206 #define SDMA5_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1207 //SDMA5_GFX_PREEMPT 1208 #define SDMA5_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1209 #define SDMA5_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1210 //SDMA5_GFX_DUMMY_REG 1211 #define SDMA5_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1212 #define SDMA5_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1213 //SDMA5_GFX_RB_WPTR_POLL_ADDR_HI 1214 #define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1215 #define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1216 //SDMA5_GFX_RB_WPTR_POLL_ADDR_LO 1217 #define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1218 #define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1219 //SDMA5_GFX_RB_AQL_CNTL 1220 #define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1221 #define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1222 #define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1223 #define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1224 #define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1225 #define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1226 //SDMA5_GFX_MINOR_PTR_UPDATE 1227 #define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1228 #define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1229 //SDMA5_GFX_MIDCMD_DATA0 1230 #define SDMA5_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1231 #define SDMA5_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1232 //SDMA5_GFX_MIDCMD_DATA1 1233 #define SDMA5_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1234 #define SDMA5_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1235 //SDMA5_GFX_MIDCMD_DATA2 1236 #define SDMA5_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1237 #define SDMA5_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1238 //SDMA5_GFX_MIDCMD_DATA3 1239 #define SDMA5_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1240 #define SDMA5_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1241 //SDMA5_GFX_MIDCMD_DATA4 1242 #define SDMA5_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1243 #define SDMA5_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1244 //SDMA5_GFX_MIDCMD_DATA5 1245 #define SDMA5_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1246 #define SDMA5_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1247 //SDMA5_GFX_MIDCMD_DATA6 1248 #define SDMA5_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1249 #define SDMA5_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1250 //SDMA5_GFX_MIDCMD_DATA7 1251 #define SDMA5_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1252 #define SDMA5_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1253 //SDMA5_GFX_MIDCMD_DATA8 1254 #define SDMA5_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1255 #define SDMA5_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1256 //SDMA5_GFX_MIDCMD_CNTL 1257 #define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1258 #define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1259 #define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1260 #define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1261 #define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1262 #define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1263 #define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1264 #define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1265 //SDMA5_PAGE_RB_CNTL 1266 #define SDMA5_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1267 #define SDMA5_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1268 #define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1269 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1270 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1271 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1272 #define SDMA5_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1273 #define SDMA5_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1274 #define SDMA5_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1275 #define SDMA5_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1276 #define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1277 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1278 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1279 #define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1280 #define SDMA5_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1281 #define SDMA5_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1282 //SDMA5_PAGE_RB_BASE 1283 #define SDMA5_PAGE_RB_BASE__ADDR__SHIFT 0x0 1284 #define SDMA5_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1285 //SDMA5_PAGE_RB_BASE_HI 1286 #define SDMA5_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1287 #define SDMA5_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1288 //SDMA5_PAGE_RB_RPTR 1289 #define SDMA5_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1290 #define SDMA5_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1291 //SDMA5_PAGE_RB_RPTR_HI 1292 #define SDMA5_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1293 #define SDMA5_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1294 //SDMA5_PAGE_RB_WPTR 1295 #define SDMA5_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1296 #define SDMA5_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1297 //SDMA5_PAGE_RB_WPTR_HI 1298 #define SDMA5_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1299 #define SDMA5_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1300 //SDMA5_PAGE_RB_WPTR_POLL_CNTL 1301 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1302 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1303 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1304 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1305 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1306 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1307 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1308 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1309 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1310 #define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1311 //SDMA5_PAGE_RB_RPTR_ADDR_HI 1312 #define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1313 #define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1314 //SDMA5_PAGE_RB_RPTR_ADDR_LO 1315 #define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1316 #define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1317 #define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1318 #define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1319 //SDMA5_PAGE_IB_CNTL 1320 #define SDMA5_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1321 #define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1322 #define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1323 #define SDMA5_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1324 #define SDMA5_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1325 #define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1326 #define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1327 #define SDMA5_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1328 //SDMA5_PAGE_IB_RPTR 1329 #define SDMA5_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1330 #define SDMA5_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1331 //SDMA5_PAGE_IB_OFFSET 1332 #define SDMA5_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1333 #define SDMA5_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1334 //SDMA5_PAGE_IB_BASE_LO 1335 #define SDMA5_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1336 #define SDMA5_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1337 //SDMA5_PAGE_IB_BASE_HI 1338 #define SDMA5_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1339 #define SDMA5_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1340 //SDMA5_PAGE_IB_SIZE 1341 #define SDMA5_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1342 #define SDMA5_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1343 //SDMA5_PAGE_SKIP_CNTL 1344 #define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1345 #define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1346 //SDMA5_PAGE_CONTEXT_STATUS 1347 #define SDMA5_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1348 #define SDMA5_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1349 #define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1350 #define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1351 #define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1352 #define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1353 #define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1354 #define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1355 #define SDMA5_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1356 #define SDMA5_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1357 #define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1358 #define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1359 #define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1360 #define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1361 #define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1362 #define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1363 //SDMA5_PAGE_DOORBELL 1364 #define SDMA5_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1365 #define SDMA5_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1366 #define SDMA5_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1367 #define SDMA5_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1368 //SDMA5_PAGE_STATUS 1369 #define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1370 #define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1371 #define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1372 #define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1373 //SDMA5_PAGE_DOORBELL_LOG 1374 #define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1375 #define SDMA5_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1376 #define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1377 #define SDMA5_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1378 //SDMA5_PAGE_WATERMARK 1379 #define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1380 #define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1381 #define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1382 #define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1383 //SDMA5_PAGE_DOORBELL_OFFSET 1384 #define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1385 #define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1386 //SDMA5_PAGE_CSA_ADDR_LO 1387 #define SDMA5_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1388 #define SDMA5_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1389 //SDMA5_PAGE_CSA_ADDR_HI 1390 #define SDMA5_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1391 #define SDMA5_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1392 //SDMA5_PAGE_IB_SUB_REMAIN 1393 #define SDMA5_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1394 #define SDMA5_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1395 //SDMA5_PAGE_PREEMPT 1396 #define SDMA5_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1397 #define SDMA5_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1398 //SDMA5_PAGE_DUMMY_REG 1399 #define SDMA5_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1400 #define SDMA5_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1401 //SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI 1402 #define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1403 #define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1404 //SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO 1405 #define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1406 #define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1407 //SDMA5_PAGE_RB_AQL_CNTL 1408 #define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1409 #define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1410 #define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1411 #define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1412 #define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1413 #define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1414 //SDMA5_PAGE_MINOR_PTR_UPDATE 1415 #define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1416 #define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1417 //SDMA5_PAGE_MIDCMD_DATA0 1418 #define SDMA5_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1419 #define SDMA5_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1420 //SDMA5_PAGE_MIDCMD_DATA1 1421 #define SDMA5_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1422 #define SDMA5_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1423 //SDMA5_PAGE_MIDCMD_DATA2 1424 #define SDMA5_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1425 #define SDMA5_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1426 //SDMA5_PAGE_MIDCMD_DATA3 1427 #define SDMA5_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1428 #define SDMA5_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1429 //SDMA5_PAGE_MIDCMD_DATA4 1430 #define SDMA5_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1431 #define SDMA5_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1432 //SDMA5_PAGE_MIDCMD_DATA5 1433 #define SDMA5_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1434 #define SDMA5_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1435 //SDMA5_PAGE_MIDCMD_DATA6 1436 #define SDMA5_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1437 #define SDMA5_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1438 //SDMA5_PAGE_MIDCMD_DATA7 1439 #define SDMA5_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1440 #define SDMA5_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1441 //SDMA5_PAGE_MIDCMD_DATA8 1442 #define SDMA5_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1443 #define SDMA5_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1444 //SDMA5_PAGE_MIDCMD_CNTL 1445 #define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1446 #define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1447 #define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1448 #define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1449 #define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1450 #define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1451 #define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1452 #define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1453 //SDMA5_RLC0_RB_CNTL 1454 #define SDMA5_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1455 #define SDMA5_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1456 #define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1457 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1458 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1459 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1460 #define SDMA5_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1461 #define SDMA5_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1462 #define SDMA5_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1463 #define SDMA5_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1464 #define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1465 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1466 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1467 #define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1468 #define SDMA5_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1469 #define SDMA5_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1470 //SDMA5_RLC0_RB_BASE 1471 #define SDMA5_RLC0_RB_BASE__ADDR__SHIFT 0x0 1472 #define SDMA5_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1473 //SDMA5_RLC0_RB_BASE_HI 1474 #define SDMA5_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1475 #define SDMA5_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1476 //SDMA5_RLC0_RB_RPTR 1477 #define SDMA5_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1478 #define SDMA5_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1479 //SDMA5_RLC0_RB_RPTR_HI 1480 #define SDMA5_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1481 #define SDMA5_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1482 //SDMA5_RLC0_RB_WPTR 1483 #define SDMA5_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1484 #define SDMA5_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1485 //SDMA5_RLC0_RB_WPTR_HI 1486 #define SDMA5_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1487 #define SDMA5_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1488 //SDMA5_RLC0_RB_WPTR_POLL_CNTL 1489 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1490 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1491 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1492 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1493 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1494 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1495 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1496 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1497 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1498 #define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1499 //SDMA5_RLC0_RB_RPTR_ADDR_HI 1500 #define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1501 #define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1502 //SDMA5_RLC0_RB_RPTR_ADDR_LO 1503 #define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1504 #define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1505 #define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1506 #define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1507 //SDMA5_RLC0_IB_CNTL 1508 #define SDMA5_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1509 #define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1510 #define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1511 #define SDMA5_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1512 #define SDMA5_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1513 #define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1514 #define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1515 #define SDMA5_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1516 //SDMA5_RLC0_IB_RPTR 1517 #define SDMA5_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1518 #define SDMA5_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1519 //SDMA5_RLC0_IB_OFFSET 1520 #define SDMA5_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1521 #define SDMA5_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1522 //SDMA5_RLC0_IB_BASE_LO 1523 #define SDMA5_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1524 #define SDMA5_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1525 //SDMA5_RLC0_IB_BASE_HI 1526 #define SDMA5_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1527 #define SDMA5_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1528 //SDMA5_RLC0_IB_SIZE 1529 #define SDMA5_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1530 #define SDMA5_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1531 //SDMA5_RLC0_SKIP_CNTL 1532 #define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1533 #define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1534 //SDMA5_RLC0_CONTEXT_STATUS 1535 #define SDMA5_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1536 #define SDMA5_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1537 #define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1538 #define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1539 #define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1540 #define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1541 #define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1542 #define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1543 #define SDMA5_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1544 #define SDMA5_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1545 #define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1546 #define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1547 #define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1548 #define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1549 #define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1550 #define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1551 //SDMA5_RLC0_DOORBELL 1552 #define SDMA5_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1553 #define SDMA5_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1554 #define SDMA5_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1555 #define SDMA5_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1556 //SDMA5_RLC0_STATUS 1557 #define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1558 #define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1559 #define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1560 #define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1561 //SDMA5_RLC0_DOORBELL_LOG 1562 #define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1563 #define SDMA5_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1564 #define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1565 #define SDMA5_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1566 //SDMA5_RLC0_WATERMARK 1567 #define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1568 #define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1569 #define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1570 #define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1571 //SDMA5_RLC0_DOORBELL_OFFSET 1572 #define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1573 #define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1574 //SDMA5_RLC0_CSA_ADDR_LO 1575 #define SDMA5_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1576 #define SDMA5_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1577 //SDMA5_RLC0_CSA_ADDR_HI 1578 #define SDMA5_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1579 #define SDMA5_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1580 //SDMA5_RLC0_IB_SUB_REMAIN 1581 #define SDMA5_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1582 #define SDMA5_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1583 //SDMA5_RLC0_PREEMPT 1584 #define SDMA5_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1585 #define SDMA5_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1586 //SDMA5_RLC0_DUMMY_REG 1587 #define SDMA5_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1588 #define SDMA5_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1589 //SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI 1590 #define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1591 #define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1592 //SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO 1593 #define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1594 #define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1595 //SDMA5_RLC0_RB_AQL_CNTL 1596 #define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1597 #define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1598 #define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1599 #define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1600 #define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1601 #define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1602 //SDMA5_RLC0_MINOR_PTR_UPDATE 1603 #define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1604 #define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1605 //SDMA5_RLC0_MIDCMD_DATA0 1606 #define SDMA5_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1607 #define SDMA5_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1608 //SDMA5_RLC0_MIDCMD_DATA1 1609 #define SDMA5_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1610 #define SDMA5_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1611 //SDMA5_RLC0_MIDCMD_DATA2 1612 #define SDMA5_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1613 #define SDMA5_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1614 //SDMA5_RLC0_MIDCMD_DATA3 1615 #define SDMA5_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1616 #define SDMA5_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1617 //SDMA5_RLC0_MIDCMD_DATA4 1618 #define SDMA5_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1619 #define SDMA5_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1620 //SDMA5_RLC0_MIDCMD_DATA5 1621 #define SDMA5_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1622 #define SDMA5_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1623 //SDMA5_RLC0_MIDCMD_DATA6 1624 #define SDMA5_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1625 #define SDMA5_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1626 //SDMA5_RLC0_MIDCMD_DATA7 1627 #define SDMA5_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1628 #define SDMA5_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1629 //SDMA5_RLC0_MIDCMD_DATA8 1630 #define SDMA5_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1631 #define SDMA5_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1632 //SDMA5_RLC0_MIDCMD_CNTL 1633 #define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1634 #define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1635 #define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1636 #define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1637 #define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1638 #define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1639 #define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1640 #define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1641 //SDMA5_RLC1_RB_CNTL 1642 #define SDMA5_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1643 #define SDMA5_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1644 #define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1645 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1646 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1647 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1648 #define SDMA5_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1649 #define SDMA5_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1650 #define SDMA5_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1651 #define SDMA5_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1652 #define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1653 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1654 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1655 #define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1656 #define SDMA5_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1657 #define SDMA5_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1658 //SDMA5_RLC1_RB_BASE 1659 #define SDMA5_RLC1_RB_BASE__ADDR__SHIFT 0x0 1660 #define SDMA5_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1661 //SDMA5_RLC1_RB_BASE_HI 1662 #define SDMA5_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1663 #define SDMA5_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1664 //SDMA5_RLC1_RB_RPTR 1665 #define SDMA5_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1666 #define SDMA5_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1667 //SDMA5_RLC1_RB_RPTR_HI 1668 #define SDMA5_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1669 #define SDMA5_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1670 //SDMA5_RLC1_RB_WPTR 1671 #define SDMA5_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1672 #define SDMA5_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1673 //SDMA5_RLC1_RB_WPTR_HI 1674 #define SDMA5_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1675 #define SDMA5_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1676 //SDMA5_RLC1_RB_WPTR_POLL_CNTL 1677 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1678 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1679 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1680 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1681 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1682 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1683 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1684 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1685 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1686 #define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1687 //SDMA5_RLC1_RB_RPTR_ADDR_HI 1688 #define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1689 #define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1690 //SDMA5_RLC1_RB_RPTR_ADDR_LO 1691 #define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1692 #define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1693 #define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1694 #define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1695 //SDMA5_RLC1_IB_CNTL 1696 #define SDMA5_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1697 #define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1698 #define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1699 #define SDMA5_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1700 #define SDMA5_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1701 #define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1702 #define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1703 #define SDMA5_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1704 //SDMA5_RLC1_IB_RPTR 1705 #define SDMA5_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1706 #define SDMA5_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1707 //SDMA5_RLC1_IB_OFFSET 1708 #define SDMA5_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1709 #define SDMA5_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1710 //SDMA5_RLC1_IB_BASE_LO 1711 #define SDMA5_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1712 #define SDMA5_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1713 //SDMA5_RLC1_IB_BASE_HI 1714 #define SDMA5_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1715 #define SDMA5_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1716 //SDMA5_RLC1_IB_SIZE 1717 #define SDMA5_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1718 #define SDMA5_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1719 //SDMA5_RLC1_SKIP_CNTL 1720 #define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1721 #define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1722 //SDMA5_RLC1_CONTEXT_STATUS 1723 #define SDMA5_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1724 #define SDMA5_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1725 #define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1726 #define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1727 #define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1728 #define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1729 #define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1730 #define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1731 #define SDMA5_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1732 #define SDMA5_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1733 #define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1734 #define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1735 #define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1736 #define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1737 #define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1738 #define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1739 //SDMA5_RLC1_DOORBELL 1740 #define SDMA5_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1741 #define SDMA5_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1742 #define SDMA5_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1743 #define SDMA5_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1744 //SDMA5_RLC1_STATUS 1745 #define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1746 #define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1747 #define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1748 #define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1749 //SDMA5_RLC1_DOORBELL_LOG 1750 #define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1751 #define SDMA5_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1752 #define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1753 #define SDMA5_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1754 //SDMA5_RLC1_WATERMARK 1755 #define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1756 #define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1757 #define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1758 #define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1759 //SDMA5_RLC1_DOORBELL_OFFSET 1760 #define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1761 #define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1762 //SDMA5_RLC1_CSA_ADDR_LO 1763 #define SDMA5_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1764 #define SDMA5_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1765 //SDMA5_RLC1_CSA_ADDR_HI 1766 #define SDMA5_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1767 #define SDMA5_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1768 //SDMA5_RLC1_IB_SUB_REMAIN 1769 #define SDMA5_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1770 #define SDMA5_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1771 //SDMA5_RLC1_PREEMPT 1772 #define SDMA5_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1773 #define SDMA5_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1774 //SDMA5_RLC1_DUMMY_REG 1775 #define SDMA5_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1776 #define SDMA5_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1777 //SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI 1778 #define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1779 #define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1780 //SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO 1781 #define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1782 #define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1783 //SDMA5_RLC1_RB_AQL_CNTL 1784 #define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1785 #define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1786 #define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1787 #define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1788 #define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1789 #define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1790 //SDMA5_RLC1_MINOR_PTR_UPDATE 1791 #define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1792 #define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1793 //SDMA5_RLC1_MIDCMD_DATA0 1794 #define SDMA5_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1795 #define SDMA5_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1796 //SDMA5_RLC1_MIDCMD_DATA1 1797 #define SDMA5_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1798 #define SDMA5_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1799 //SDMA5_RLC1_MIDCMD_DATA2 1800 #define SDMA5_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1801 #define SDMA5_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1802 //SDMA5_RLC1_MIDCMD_DATA3 1803 #define SDMA5_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1804 #define SDMA5_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1805 //SDMA5_RLC1_MIDCMD_DATA4 1806 #define SDMA5_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1807 #define SDMA5_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1808 //SDMA5_RLC1_MIDCMD_DATA5 1809 #define SDMA5_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1810 #define SDMA5_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1811 //SDMA5_RLC1_MIDCMD_DATA6 1812 #define SDMA5_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1813 #define SDMA5_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1814 //SDMA5_RLC1_MIDCMD_DATA7 1815 #define SDMA5_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1816 #define SDMA5_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1817 //SDMA5_RLC1_MIDCMD_DATA8 1818 #define SDMA5_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1819 #define SDMA5_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1820 //SDMA5_RLC1_MIDCMD_CNTL 1821 #define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1822 #define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1823 #define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1824 #define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1825 #define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1826 #define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1827 #define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1828 #define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1829 //SDMA5_RLC2_RB_CNTL 1830 #define SDMA5_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1831 #define SDMA5_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1832 #define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1833 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1834 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1835 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1836 #define SDMA5_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1837 #define SDMA5_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1838 #define SDMA5_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1839 #define SDMA5_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1840 #define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1841 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1842 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1843 #define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1844 #define SDMA5_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1845 #define SDMA5_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1846 //SDMA5_RLC2_RB_BASE 1847 #define SDMA5_RLC2_RB_BASE__ADDR__SHIFT 0x0 1848 #define SDMA5_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1849 //SDMA5_RLC2_RB_BASE_HI 1850 #define SDMA5_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1851 #define SDMA5_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1852 //SDMA5_RLC2_RB_RPTR 1853 #define SDMA5_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1854 #define SDMA5_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1855 //SDMA5_RLC2_RB_RPTR_HI 1856 #define SDMA5_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1857 #define SDMA5_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1858 //SDMA5_RLC2_RB_WPTR 1859 #define SDMA5_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1860 #define SDMA5_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1861 //SDMA5_RLC2_RB_WPTR_HI 1862 #define SDMA5_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1863 #define SDMA5_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1864 //SDMA5_RLC2_RB_WPTR_POLL_CNTL 1865 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1866 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1867 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1868 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1869 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1870 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1871 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1872 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1873 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1874 #define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1875 //SDMA5_RLC2_RB_RPTR_ADDR_HI 1876 #define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1877 #define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1878 //SDMA5_RLC2_RB_RPTR_ADDR_LO 1879 #define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1880 #define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1881 #define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1882 #define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1883 //SDMA5_RLC2_IB_CNTL 1884 #define SDMA5_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1885 #define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1886 #define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1887 #define SDMA5_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1888 #define SDMA5_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1889 #define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1890 #define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1891 #define SDMA5_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1892 //SDMA5_RLC2_IB_RPTR 1893 #define SDMA5_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1894 #define SDMA5_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1895 //SDMA5_RLC2_IB_OFFSET 1896 #define SDMA5_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1897 #define SDMA5_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1898 //SDMA5_RLC2_IB_BASE_LO 1899 #define SDMA5_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1900 #define SDMA5_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1901 //SDMA5_RLC2_IB_BASE_HI 1902 #define SDMA5_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1903 #define SDMA5_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1904 //SDMA5_RLC2_IB_SIZE 1905 #define SDMA5_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1906 #define SDMA5_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1907 //SDMA5_RLC2_SKIP_CNTL 1908 #define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1909 #define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1910 //SDMA5_RLC2_CONTEXT_STATUS 1911 #define SDMA5_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1912 #define SDMA5_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1913 #define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1914 #define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1915 #define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1916 #define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1917 #define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1918 #define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1919 #define SDMA5_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1920 #define SDMA5_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1921 #define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1922 #define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1923 #define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1924 #define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1925 #define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1926 #define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1927 //SDMA5_RLC2_DOORBELL 1928 #define SDMA5_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1929 #define SDMA5_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1930 #define SDMA5_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1931 #define SDMA5_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1932 //SDMA5_RLC2_STATUS 1933 #define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1934 #define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1935 #define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1936 #define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1937 //SDMA5_RLC2_DOORBELL_LOG 1938 #define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1939 #define SDMA5_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1940 #define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1941 #define SDMA5_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1942 //SDMA5_RLC2_WATERMARK 1943 #define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1944 #define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1945 #define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1946 #define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1947 //SDMA5_RLC2_DOORBELL_OFFSET 1948 #define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1949 #define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1950 //SDMA5_RLC2_CSA_ADDR_LO 1951 #define SDMA5_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1952 #define SDMA5_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1953 //SDMA5_RLC2_CSA_ADDR_HI 1954 #define SDMA5_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1955 #define SDMA5_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1956 //SDMA5_RLC2_IB_SUB_REMAIN 1957 #define SDMA5_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1958 #define SDMA5_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1959 //SDMA5_RLC2_PREEMPT 1960 #define SDMA5_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1961 #define SDMA5_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1962 //SDMA5_RLC2_DUMMY_REG 1963 #define SDMA5_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1964 #define SDMA5_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1965 //SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI 1966 #define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1967 #define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1968 //SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO 1969 #define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1970 #define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1971 //SDMA5_RLC2_RB_AQL_CNTL 1972 #define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1973 #define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1974 #define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1975 #define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1976 #define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1977 #define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1978 //SDMA5_RLC2_MINOR_PTR_UPDATE 1979 #define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1980 #define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1981 //SDMA5_RLC2_MIDCMD_DATA0 1982 #define SDMA5_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 1983 #define SDMA5_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1984 //SDMA5_RLC2_MIDCMD_DATA1 1985 #define SDMA5_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 1986 #define SDMA5_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1987 //SDMA5_RLC2_MIDCMD_DATA2 1988 #define SDMA5_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 1989 #define SDMA5_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1990 //SDMA5_RLC2_MIDCMD_DATA3 1991 #define SDMA5_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 1992 #define SDMA5_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1993 //SDMA5_RLC2_MIDCMD_DATA4 1994 #define SDMA5_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 1995 #define SDMA5_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1996 //SDMA5_RLC2_MIDCMD_DATA5 1997 #define SDMA5_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 1998 #define SDMA5_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1999 //SDMA5_RLC2_MIDCMD_DATA6 2000 #define SDMA5_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2001 #define SDMA5_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2002 //SDMA5_RLC2_MIDCMD_DATA7 2003 #define SDMA5_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2004 #define SDMA5_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2005 //SDMA5_RLC2_MIDCMD_DATA8 2006 #define SDMA5_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2007 #define SDMA5_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2008 //SDMA5_RLC2_MIDCMD_CNTL 2009 #define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2010 #define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2011 #define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2012 #define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2013 #define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2014 #define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2015 #define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2016 #define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2017 //SDMA5_RLC3_RB_CNTL 2018 #define SDMA5_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2019 #define SDMA5_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2020 #define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2021 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2022 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2023 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2024 #define SDMA5_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2025 #define SDMA5_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2026 #define SDMA5_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2027 #define SDMA5_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2028 #define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2029 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2030 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2031 #define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2032 #define SDMA5_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2033 #define SDMA5_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2034 //SDMA5_RLC3_RB_BASE 2035 #define SDMA5_RLC3_RB_BASE__ADDR__SHIFT 0x0 2036 #define SDMA5_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2037 //SDMA5_RLC3_RB_BASE_HI 2038 #define SDMA5_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2039 #define SDMA5_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2040 //SDMA5_RLC3_RB_RPTR 2041 #define SDMA5_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2042 #define SDMA5_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2043 //SDMA5_RLC3_RB_RPTR_HI 2044 #define SDMA5_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2045 #define SDMA5_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2046 //SDMA5_RLC3_RB_WPTR 2047 #define SDMA5_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2048 #define SDMA5_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2049 //SDMA5_RLC3_RB_WPTR_HI 2050 #define SDMA5_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2051 #define SDMA5_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2052 //SDMA5_RLC3_RB_WPTR_POLL_CNTL 2053 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2054 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2055 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2056 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2057 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2058 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2059 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2060 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2061 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2062 #define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2063 //SDMA5_RLC3_RB_RPTR_ADDR_HI 2064 #define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2065 #define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2066 //SDMA5_RLC3_RB_RPTR_ADDR_LO 2067 #define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2068 #define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2069 #define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2070 #define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2071 //SDMA5_RLC3_IB_CNTL 2072 #define SDMA5_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2073 #define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2074 #define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2075 #define SDMA5_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2076 #define SDMA5_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2077 #define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2078 #define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2079 #define SDMA5_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2080 //SDMA5_RLC3_IB_RPTR 2081 #define SDMA5_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2082 #define SDMA5_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2083 //SDMA5_RLC3_IB_OFFSET 2084 #define SDMA5_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2085 #define SDMA5_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2086 //SDMA5_RLC3_IB_BASE_LO 2087 #define SDMA5_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2088 #define SDMA5_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2089 //SDMA5_RLC3_IB_BASE_HI 2090 #define SDMA5_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2091 #define SDMA5_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2092 //SDMA5_RLC3_IB_SIZE 2093 #define SDMA5_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2094 #define SDMA5_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2095 //SDMA5_RLC3_SKIP_CNTL 2096 #define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2097 #define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2098 //SDMA5_RLC3_CONTEXT_STATUS 2099 #define SDMA5_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2100 #define SDMA5_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2101 #define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2102 #define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2103 #define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2104 #define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2105 #define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2106 #define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2107 #define SDMA5_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2108 #define SDMA5_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2109 #define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2110 #define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2111 #define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2112 #define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2113 #define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2114 #define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2115 //SDMA5_RLC3_DOORBELL 2116 #define SDMA5_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2117 #define SDMA5_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2118 #define SDMA5_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2119 #define SDMA5_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2120 //SDMA5_RLC3_STATUS 2121 #define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2122 #define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2123 #define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2124 #define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2125 //SDMA5_RLC3_DOORBELL_LOG 2126 #define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2127 #define SDMA5_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2128 #define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2129 #define SDMA5_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2130 //SDMA5_RLC3_WATERMARK 2131 #define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2132 #define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2133 #define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2134 #define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2135 //SDMA5_RLC3_DOORBELL_OFFSET 2136 #define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2137 #define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2138 //SDMA5_RLC3_CSA_ADDR_LO 2139 #define SDMA5_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2140 #define SDMA5_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2141 //SDMA5_RLC3_CSA_ADDR_HI 2142 #define SDMA5_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2143 #define SDMA5_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2144 //SDMA5_RLC3_IB_SUB_REMAIN 2145 #define SDMA5_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2146 #define SDMA5_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2147 //SDMA5_RLC3_PREEMPT 2148 #define SDMA5_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2149 #define SDMA5_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2150 //SDMA5_RLC3_DUMMY_REG 2151 #define SDMA5_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2152 #define SDMA5_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2153 //SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI 2154 #define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2155 #define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2156 //SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO 2157 #define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2158 #define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2159 //SDMA5_RLC3_RB_AQL_CNTL 2160 #define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2161 #define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2162 #define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2163 #define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2164 #define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2165 #define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2166 //SDMA5_RLC3_MINOR_PTR_UPDATE 2167 #define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2168 #define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2169 //SDMA5_RLC3_MIDCMD_DATA0 2170 #define SDMA5_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2171 #define SDMA5_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2172 //SDMA5_RLC3_MIDCMD_DATA1 2173 #define SDMA5_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2174 #define SDMA5_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2175 //SDMA5_RLC3_MIDCMD_DATA2 2176 #define SDMA5_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2177 #define SDMA5_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2178 //SDMA5_RLC3_MIDCMD_DATA3 2179 #define SDMA5_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2180 #define SDMA5_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2181 //SDMA5_RLC3_MIDCMD_DATA4 2182 #define SDMA5_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2183 #define SDMA5_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2184 //SDMA5_RLC3_MIDCMD_DATA5 2185 #define SDMA5_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2186 #define SDMA5_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2187 //SDMA5_RLC3_MIDCMD_DATA6 2188 #define SDMA5_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2189 #define SDMA5_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2190 //SDMA5_RLC3_MIDCMD_DATA7 2191 #define SDMA5_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2192 #define SDMA5_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2193 //SDMA5_RLC3_MIDCMD_DATA8 2194 #define SDMA5_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2195 #define SDMA5_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2196 //SDMA5_RLC3_MIDCMD_CNTL 2197 #define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2198 #define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2199 #define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2200 #define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2201 #define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2202 #define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2203 #define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2204 #define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2205 //SDMA5_RLC4_RB_CNTL 2206 #define SDMA5_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2207 #define SDMA5_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2208 #define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2209 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2210 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2211 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2212 #define SDMA5_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2213 #define SDMA5_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2214 #define SDMA5_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2215 #define SDMA5_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2216 #define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2217 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2218 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2219 #define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2220 #define SDMA5_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2221 #define SDMA5_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2222 //SDMA5_RLC4_RB_BASE 2223 #define SDMA5_RLC4_RB_BASE__ADDR__SHIFT 0x0 2224 #define SDMA5_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2225 //SDMA5_RLC4_RB_BASE_HI 2226 #define SDMA5_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2227 #define SDMA5_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2228 //SDMA5_RLC4_RB_RPTR 2229 #define SDMA5_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2230 #define SDMA5_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2231 //SDMA5_RLC4_RB_RPTR_HI 2232 #define SDMA5_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2233 #define SDMA5_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2234 //SDMA5_RLC4_RB_WPTR 2235 #define SDMA5_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2236 #define SDMA5_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2237 //SDMA5_RLC4_RB_WPTR_HI 2238 #define SDMA5_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2239 #define SDMA5_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2240 //SDMA5_RLC4_RB_WPTR_POLL_CNTL 2241 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2242 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2243 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2244 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2245 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2246 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2247 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2248 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2249 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2250 #define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2251 //SDMA5_RLC4_RB_RPTR_ADDR_HI 2252 #define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2253 #define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2254 //SDMA5_RLC4_RB_RPTR_ADDR_LO 2255 #define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2256 #define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2257 #define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2258 #define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2259 //SDMA5_RLC4_IB_CNTL 2260 #define SDMA5_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2261 #define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2262 #define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2263 #define SDMA5_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2264 #define SDMA5_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2265 #define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2266 #define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2267 #define SDMA5_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2268 //SDMA5_RLC4_IB_RPTR 2269 #define SDMA5_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2270 #define SDMA5_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2271 //SDMA5_RLC4_IB_OFFSET 2272 #define SDMA5_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2273 #define SDMA5_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2274 //SDMA5_RLC4_IB_BASE_LO 2275 #define SDMA5_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2276 #define SDMA5_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2277 //SDMA5_RLC4_IB_BASE_HI 2278 #define SDMA5_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2279 #define SDMA5_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2280 //SDMA5_RLC4_IB_SIZE 2281 #define SDMA5_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2282 #define SDMA5_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2283 //SDMA5_RLC4_SKIP_CNTL 2284 #define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2285 #define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2286 //SDMA5_RLC4_CONTEXT_STATUS 2287 #define SDMA5_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2288 #define SDMA5_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2289 #define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2290 #define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2291 #define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2292 #define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2293 #define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2294 #define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2295 #define SDMA5_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2296 #define SDMA5_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2297 #define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2298 #define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2299 #define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2300 #define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2301 #define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2302 #define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2303 //SDMA5_RLC4_DOORBELL 2304 #define SDMA5_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2305 #define SDMA5_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2306 #define SDMA5_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2307 #define SDMA5_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2308 //SDMA5_RLC4_STATUS 2309 #define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2310 #define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2311 #define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2312 #define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2313 //SDMA5_RLC4_DOORBELL_LOG 2314 #define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2315 #define SDMA5_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2316 #define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2317 #define SDMA5_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2318 //SDMA5_RLC4_WATERMARK 2319 #define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2320 #define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2321 #define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2322 #define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2323 //SDMA5_RLC4_DOORBELL_OFFSET 2324 #define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2325 #define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2326 //SDMA5_RLC4_CSA_ADDR_LO 2327 #define SDMA5_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2328 #define SDMA5_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2329 //SDMA5_RLC4_CSA_ADDR_HI 2330 #define SDMA5_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2331 #define SDMA5_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2332 //SDMA5_RLC4_IB_SUB_REMAIN 2333 #define SDMA5_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2334 #define SDMA5_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2335 //SDMA5_RLC4_PREEMPT 2336 #define SDMA5_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2337 #define SDMA5_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2338 //SDMA5_RLC4_DUMMY_REG 2339 #define SDMA5_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2340 #define SDMA5_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2341 //SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI 2342 #define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2343 #define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2344 //SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO 2345 #define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2346 #define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2347 //SDMA5_RLC4_RB_AQL_CNTL 2348 #define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2349 #define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2350 #define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2351 #define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2352 #define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2353 #define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2354 //SDMA5_RLC4_MINOR_PTR_UPDATE 2355 #define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2356 #define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2357 //SDMA5_RLC4_MIDCMD_DATA0 2358 #define SDMA5_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2359 #define SDMA5_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2360 //SDMA5_RLC4_MIDCMD_DATA1 2361 #define SDMA5_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2362 #define SDMA5_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2363 //SDMA5_RLC4_MIDCMD_DATA2 2364 #define SDMA5_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2365 #define SDMA5_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2366 //SDMA5_RLC4_MIDCMD_DATA3 2367 #define SDMA5_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2368 #define SDMA5_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2369 //SDMA5_RLC4_MIDCMD_DATA4 2370 #define SDMA5_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2371 #define SDMA5_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2372 //SDMA5_RLC4_MIDCMD_DATA5 2373 #define SDMA5_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2374 #define SDMA5_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2375 //SDMA5_RLC4_MIDCMD_DATA6 2376 #define SDMA5_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2377 #define SDMA5_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2378 //SDMA5_RLC4_MIDCMD_DATA7 2379 #define SDMA5_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2380 #define SDMA5_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2381 //SDMA5_RLC4_MIDCMD_DATA8 2382 #define SDMA5_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2383 #define SDMA5_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2384 //SDMA5_RLC4_MIDCMD_CNTL 2385 #define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2386 #define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2387 #define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2388 #define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2389 #define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2390 #define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2391 #define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2392 #define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2393 //SDMA5_RLC5_RB_CNTL 2394 #define SDMA5_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2395 #define SDMA5_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2396 #define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2397 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2398 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2399 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2400 #define SDMA5_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2401 #define SDMA5_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2402 #define SDMA5_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2403 #define SDMA5_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2404 #define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2405 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2406 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2407 #define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2408 #define SDMA5_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2409 #define SDMA5_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2410 //SDMA5_RLC5_RB_BASE 2411 #define SDMA5_RLC5_RB_BASE__ADDR__SHIFT 0x0 2412 #define SDMA5_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2413 //SDMA5_RLC5_RB_BASE_HI 2414 #define SDMA5_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2415 #define SDMA5_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2416 //SDMA5_RLC5_RB_RPTR 2417 #define SDMA5_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2418 #define SDMA5_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2419 //SDMA5_RLC5_RB_RPTR_HI 2420 #define SDMA5_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2421 #define SDMA5_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2422 //SDMA5_RLC5_RB_WPTR 2423 #define SDMA5_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2424 #define SDMA5_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2425 //SDMA5_RLC5_RB_WPTR_HI 2426 #define SDMA5_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2427 #define SDMA5_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2428 //SDMA5_RLC5_RB_WPTR_POLL_CNTL 2429 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2430 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2431 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2432 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2433 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2434 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2435 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2436 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2437 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2438 #define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2439 //SDMA5_RLC5_RB_RPTR_ADDR_HI 2440 #define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2441 #define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2442 //SDMA5_RLC5_RB_RPTR_ADDR_LO 2443 #define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2444 #define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2445 #define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2446 #define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2447 //SDMA5_RLC5_IB_CNTL 2448 #define SDMA5_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2449 #define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2450 #define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2451 #define SDMA5_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2452 #define SDMA5_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2453 #define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2454 #define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2455 #define SDMA5_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2456 //SDMA5_RLC5_IB_RPTR 2457 #define SDMA5_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2458 #define SDMA5_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2459 //SDMA5_RLC5_IB_OFFSET 2460 #define SDMA5_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2461 #define SDMA5_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2462 //SDMA5_RLC5_IB_BASE_LO 2463 #define SDMA5_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2464 #define SDMA5_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2465 //SDMA5_RLC5_IB_BASE_HI 2466 #define SDMA5_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2467 #define SDMA5_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2468 //SDMA5_RLC5_IB_SIZE 2469 #define SDMA5_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2470 #define SDMA5_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2471 //SDMA5_RLC5_SKIP_CNTL 2472 #define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2473 #define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2474 //SDMA5_RLC5_CONTEXT_STATUS 2475 #define SDMA5_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2476 #define SDMA5_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2477 #define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2478 #define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2479 #define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2480 #define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2481 #define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2482 #define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2483 #define SDMA5_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2484 #define SDMA5_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2485 #define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2486 #define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2487 #define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2488 #define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2489 #define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2490 #define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2491 //SDMA5_RLC5_DOORBELL 2492 #define SDMA5_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2493 #define SDMA5_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2494 #define SDMA5_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2495 #define SDMA5_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2496 //SDMA5_RLC5_STATUS 2497 #define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2498 #define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2499 #define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2500 #define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2501 //SDMA5_RLC5_DOORBELL_LOG 2502 #define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2503 #define SDMA5_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2504 #define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2505 #define SDMA5_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2506 //SDMA5_RLC5_WATERMARK 2507 #define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2508 #define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2509 #define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2510 #define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2511 //SDMA5_RLC5_DOORBELL_OFFSET 2512 #define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2513 #define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2514 //SDMA5_RLC5_CSA_ADDR_LO 2515 #define SDMA5_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2516 #define SDMA5_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2517 //SDMA5_RLC5_CSA_ADDR_HI 2518 #define SDMA5_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2519 #define SDMA5_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2520 //SDMA5_RLC5_IB_SUB_REMAIN 2521 #define SDMA5_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2522 #define SDMA5_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2523 //SDMA5_RLC5_PREEMPT 2524 #define SDMA5_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2525 #define SDMA5_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2526 //SDMA5_RLC5_DUMMY_REG 2527 #define SDMA5_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2528 #define SDMA5_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2529 //SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI 2530 #define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2531 #define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2532 //SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO 2533 #define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2534 #define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2535 //SDMA5_RLC5_RB_AQL_CNTL 2536 #define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2537 #define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2538 #define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2539 #define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2540 #define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2541 #define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2542 //SDMA5_RLC5_MINOR_PTR_UPDATE 2543 #define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2544 #define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2545 //SDMA5_RLC5_MIDCMD_DATA0 2546 #define SDMA5_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2547 #define SDMA5_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2548 //SDMA5_RLC5_MIDCMD_DATA1 2549 #define SDMA5_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2550 #define SDMA5_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2551 //SDMA5_RLC5_MIDCMD_DATA2 2552 #define SDMA5_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2553 #define SDMA5_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2554 //SDMA5_RLC5_MIDCMD_DATA3 2555 #define SDMA5_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2556 #define SDMA5_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2557 //SDMA5_RLC5_MIDCMD_DATA4 2558 #define SDMA5_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2559 #define SDMA5_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2560 //SDMA5_RLC5_MIDCMD_DATA5 2561 #define SDMA5_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2562 #define SDMA5_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2563 //SDMA5_RLC5_MIDCMD_DATA6 2564 #define SDMA5_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2565 #define SDMA5_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2566 //SDMA5_RLC5_MIDCMD_DATA7 2567 #define SDMA5_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2568 #define SDMA5_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2569 //SDMA5_RLC5_MIDCMD_DATA8 2570 #define SDMA5_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2571 #define SDMA5_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2572 //SDMA5_RLC5_MIDCMD_CNTL 2573 #define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2574 #define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2575 #define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2576 #define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2577 #define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2578 #define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2579 #define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2580 #define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2581 //SDMA5_RLC6_RB_CNTL 2582 #define SDMA5_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2583 #define SDMA5_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2584 #define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2585 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2586 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2587 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2588 #define SDMA5_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2589 #define SDMA5_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2590 #define SDMA5_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2591 #define SDMA5_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2592 #define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2593 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2594 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2595 #define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2596 #define SDMA5_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2597 #define SDMA5_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2598 //SDMA5_RLC6_RB_BASE 2599 #define SDMA5_RLC6_RB_BASE__ADDR__SHIFT 0x0 2600 #define SDMA5_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2601 //SDMA5_RLC6_RB_BASE_HI 2602 #define SDMA5_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2603 #define SDMA5_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2604 //SDMA5_RLC6_RB_RPTR 2605 #define SDMA5_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2606 #define SDMA5_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2607 //SDMA5_RLC6_RB_RPTR_HI 2608 #define SDMA5_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2609 #define SDMA5_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2610 //SDMA5_RLC6_RB_WPTR 2611 #define SDMA5_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2612 #define SDMA5_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2613 //SDMA5_RLC6_RB_WPTR_HI 2614 #define SDMA5_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2615 #define SDMA5_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2616 //SDMA5_RLC6_RB_WPTR_POLL_CNTL 2617 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2618 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2619 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2620 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2621 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2622 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2623 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2624 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2625 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2626 #define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2627 //SDMA5_RLC6_RB_RPTR_ADDR_HI 2628 #define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2629 #define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2630 //SDMA5_RLC6_RB_RPTR_ADDR_LO 2631 #define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2632 #define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2633 #define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2634 #define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2635 //SDMA5_RLC6_IB_CNTL 2636 #define SDMA5_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2637 #define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2638 #define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2639 #define SDMA5_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2640 #define SDMA5_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2641 #define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2642 #define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2643 #define SDMA5_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2644 //SDMA5_RLC6_IB_RPTR 2645 #define SDMA5_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2646 #define SDMA5_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2647 //SDMA5_RLC6_IB_OFFSET 2648 #define SDMA5_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2649 #define SDMA5_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2650 //SDMA5_RLC6_IB_BASE_LO 2651 #define SDMA5_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2652 #define SDMA5_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2653 //SDMA5_RLC6_IB_BASE_HI 2654 #define SDMA5_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2655 #define SDMA5_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2656 //SDMA5_RLC6_IB_SIZE 2657 #define SDMA5_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2658 #define SDMA5_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2659 //SDMA5_RLC6_SKIP_CNTL 2660 #define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2661 #define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2662 //SDMA5_RLC6_CONTEXT_STATUS 2663 #define SDMA5_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2664 #define SDMA5_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2665 #define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2666 #define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2667 #define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2668 #define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2669 #define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2670 #define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2671 #define SDMA5_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2672 #define SDMA5_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2673 #define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2674 #define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2675 #define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2676 #define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2677 #define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2678 #define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2679 //SDMA5_RLC6_DOORBELL 2680 #define SDMA5_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2681 #define SDMA5_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2682 #define SDMA5_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2683 #define SDMA5_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2684 //SDMA5_RLC6_STATUS 2685 #define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2686 #define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2687 #define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2688 #define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2689 //SDMA5_RLC6_DOORBELL_LOG 2690 #define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2691 #define SDMA5_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2692 #define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2693 #define SDMA5_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2694 //SDMA5_RLC6_WATERMARK 2695 #define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2696 #define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2697 #define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2698 #define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2699 //SDMA5_RLC6_DOORBELL_OFFSET 2700 #define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2701 #define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2702 //SDMA5_RLC6_CSA_ADDR_LO 2703 #define SDMA5_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2704 #define SDMA5_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2705 //SDMA5_RLC6_CSA_ADDR_HI 2706 #define SDMA5_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2707 #define SDMA5_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2708 //SDMA5_RLC6_IB_SUB_REMAIN 2709 #define SDMA5_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2710 #define SDMA5_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2711 //SDMA5_RLC6_PREEMPT 2712 #define SDMA5_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2713 #define SDMA5_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2714 //SDMA5_RLC6_DUMMY_REG 2715 #define SDMA5_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2716 #define SDMA5_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2717 //SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI 2718 #define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2719 #define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2720 //SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO 2721 #define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2722 #define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2723 //SDMA5_RLC6_RB_AQL_CNTL 2724 #define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2725 #define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2726 #define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2727 #define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2728 #define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2729 #define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2730 //SDMA5_RLC6_MINOR_PTR_UPDATE 2731 #define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2732 #define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2733 //SDMA5_RLC6_MIDCMD_DATA0 2734 #define SDMA5_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2735 #define SDMA5_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2736 //SDMA5_RLC6_MIDCMD_DATA1 2737 #define SDMA5_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2738 #define SDMA5_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2739 //SDMA5_RLC6_MIDCMD_DATA2 2740 #define SDMA5_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2741 #define SDMA5_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2742 //SDMA5_RLC6_MIDCMD_DATA3 2743 #define SDMA5_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2744 #define SDMA5_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2745 //SDMA5_RLC6_MIDCMD_DATA4 2746 #define SDMA5_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2747 #define SDMA5_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2748 //SDMA5_RLC6_MIDCMD_DATA5 2749 #define SDMA5_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2750 #define SDMA5_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2751 //SDMA5_RLC6_MIDCMD_DATA6 2752 #define SDMA5_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2753 #define SDMA5_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2754 //SDMA5_RLC6_MIDCMD_DATA7 2755 #define SDMA5_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2756 #define SDMA5_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2757 //SDMA5_RLC6_MIDCMD_DATA8 2758 #define SDMA5_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2759 #define SDMA5_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2760 //SDMA5_RLC6_MIDCMD_CNTL 2761 #define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2762 #define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2763 #define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2764 #define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2765 #define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2766 #define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2767 #define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2768 #define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2769 //SDMA5_RLC7_RB_CNTL 2770 #define SDMA5_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2771 #define SDMA5_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2772 #define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2773 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2774 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2775 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2776 #define SDMA5_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2777 #define SDMA5_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2778 #define SDMA5_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2779 #define SDMA5_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2780 #define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2781 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2782 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2783 #define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2784 #define SDMA5_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2785 #define SDMA5_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2786 //SDMA5_RLC7_RB_BASE 2787 #define SDMA5_RLC7_RB_BASE__ADDR__SHIFT 0x0 2788 #define SDMA5_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2789 //SDMA5_RLC7_RB_BASE_HI 2790 #define SDMA5_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2791 #define SDMA5_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2792 //SDMA5_RLC7_RB_RPTR 2793 #define SDMA5_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2794 #define SDMA5_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2795 //SDMA5_RLC7_RB_RPTR_HI 2796 #define SDMA5_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2797 #define SDMA5_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2798 //SDMA5_RLC7_RB_WPTR 2799 #define SDMA5_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2800 #define SDMA5_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2801 //SDMA5_RLC7_RB_WPTR_HI 2802 #define SDMA5_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2803 #define SDMA5_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2804 //SDMA5_RLC7_RB_WPTR_POLL_CNTL 2805 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2806 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2807 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2808 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2809 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2810 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2811 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2812 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2813 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2814 #define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2815 //SDMA5_RLC7_RB_RPTR_ADDR_HI 2816 #define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2817 #define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2818 //SDMA5_RLC7_RB_RPTR_ADDR_LO 2819 #define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2820 #define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2821 #define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2822 #define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2823 //SDMA5_RLC7_IB_CNTL 2824 #define SDMA5_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2825 #define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2826 #define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2827 #define SDMA5_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2828 #define SDMA5_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2829 #define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2830 #define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2831 #define SDMA5_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2832 //SDMA5_RLC7_IB_RPTR 2833 #define SDMA5_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2834 #define SDMA5_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2835 //SDMA5_RLC7_IB_OFFSET 2836 #define SDMA5_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2837 #define SDMA5_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2838 //SDMA5_RLC7_IB_BASE_LO 2839 #define SDMA5_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2840 #define SDMA5_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2841 //SDMA5_RLC7_IB_BASE_HI 2842 #define SDMA5_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2843 #define SDMA5_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2844 //SDMA5_RLC7_IB_SIZE 2845 #define SDMA5_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2846 #define SDMA5_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2847 //SDMA5_RLC7_SKIP_CNTL 2848 #define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2849 #define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2850 //SDMA5_RLC7_CONTEXT_STATUS 2851 #define SDMA5_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2852 #define SDMA5_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2853 #define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2854 #define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2855 #define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2856 #define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2857 #define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2858 #define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2859 #define SDMA5_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2860 #define SDMA5_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2861 #define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2862 #define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2863 #define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2864 #define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2865 #define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2866 #define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2867 //SDMA5_RLC7_DOORBELL 2868 #define SDMA5_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2869 #define SDMA5_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2870 #define SDMA5_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2871 #define SDMA5_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2872 //SDMA5_RLC7_STATUS 2873 #define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2874 #define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2875 #define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2876 #define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2877 //SDMA5_RLC7_DOORBELL_LOG 2878 #define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2879 #define SDMA5_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2880 #define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2881 #define SDMA5_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2882 //SDMA5_RLC7_WATERMARK 2883 #define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2884 #define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2885 #define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2886 #define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2887 //SDMA5_RLC7_DOORBELL_OFFSET 2888 #define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2889 #define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2890 //SDMA5_RLC7_CSA_ADDR_LO 2891 #define SDMA5_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2892 #define SDMA5_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2893 //SDMA5_RLC7_CSA_ADDR_HI 2894 #define SDMA5_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2895 #define SDMA5_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2896 //SDMA5_RLC7_IB_SUB_REMAIN 2897 #define SDMA5_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2898 #define SDMA5_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2899 //SDMA5_RLC7_PREEMPT 2900 #define SDMA5_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2901 #define SDMA5_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2902 //SDMA5_RLC7_DUMMY_REG 2903 #define SDMA5_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2904 #define SDMA5_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2905 //SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI 2906 #define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2907 #define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2908 //SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO 2909 #define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2910 #define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2911 //SDMA5_RLC7_RB_AQL_CNTL 2912 #define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2913 #define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2914 #define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2915 #define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2916 #define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2917 #define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2918 //SDMA5_RLC7_MINOR_PTR_UPDATE 2919 #define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2920 #define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2921 //SDMA5_RLC7_MIDCMD_DATA0 2922 #define SDMA5_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2923 #define SDMA5_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2924 //SDMA5_RLC7_MIDCMD_DATA1 2925 #define SDMA5_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2926 #define SDMA5_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2927 //SDMA5_RLC7_MIDCMD_DATA2 2928 #define SDMA5_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2929 #define SDMA5_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2930 //SDMA5_RLC7_MIDCMD_DATA3 2931 #define SDMA5_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2932 #define SDMA5_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2933 //SDMA5_RLC7_MIDCMD_DATA4 2934 #define SDMA5_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2935 #define SDMA5_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2936 //SDMA5_RLC7_MIDCMD_DATA5 2937 #define SDMA5_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2938 #define SDMA5_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2939 //SDMA5_RLC7_MIDCMD_DATA6 2940 #define SDMA5_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2941 #define SDMA5_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2942 //SDMA5_RLC7_MIDCMD_DATA7 2943 #define SDMA5_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2944 #define SDMA5_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2945 //SDMA5_RLC7_MIDCMD_DATA8 2946 #define SDMA5_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2947 #define SDMA5_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2948 //SDMA5_RLC7_MIDCMD_CNTL 2949 #define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2950 #define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2951 #define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2952 #define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2953 #define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2954 #define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2955 #define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2956 #define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2957 2958 #endif 2959
Indexes created Sat Nov 08 12:09:53 GMT 2025