| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 81 bool IgnoreNodeResults(SDNode *N) const {
138 SmallVector<SDNode*, 128> Worklist;
180 void NoteDeletion(SDNode *Old, SDNode *New) {
211 SDNode *AnalyzeNewNode(SDNode *N);
221 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
222 bool CustomWidenLowerNode(SDNode *N, EVT VT);
227 SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
231 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node)
[all...] |
| InstrEmitter.h | 47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
52 void CreateVirtualRegisters(SDNode *Node,
92 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
99 void EmitCopyToRegClassNode(SDNode *Node,
104 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
110 static unsigned CountResults(SDNode *Node);
132 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
152 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
154 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
|
| SelectionDAGPrinter.cpp | 41 return ((const SDNode *) Node)->getNumValues();
45 return ((const SDNode *) Node)->getValueType(i).getEVTString();
50 return itostr(I - SDNodeIterator::begin((const SDNode *) Node));
66 SDNode *TargetNode = *I;
80 static std::string getNodeIdentifierLabel(const SDNode *Node,
107 static std::string getSimpleNodeLabel(const SDNode *Node,
116 std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph);
117 static std::string getNodeAttributes(const SDNode *N,
141 std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
195 void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs)
[all...] |
| ScheduleDAGSDNodes.h | 1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
10 // scheduling for an SDNode-based dependency graph.
32 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
42 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
65 static bool isPassiveNode(SDNode *Node) {
86 SUnit *newSUnit(SDNode *N);
107 virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
140 const SDNode *Node;
155 const SDNode *GetNode() const
[all...] |
| SDNodeDbgValue.h | 24 class SDNode;
29 /// an SDNode, a constant, a stack location, or a virtual register.
33 SDNODE = 0, ///< Value is the result of an expression.
40 /// Returns the SDNode* for a register ref
41 SDNode *getSDNode() const {
42 assert(kind == SDNODE);
48 assert(kind == SDNODE);
70 static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo) {
88 case SDNODE:
104 SDNode *Node; ///< Valid for expressions
[all...] |
| ScheduleDAGSDNodes.cpp | 69 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
140 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
161 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
162 SDNode *GlueDestNode = Glue.getNode();
186 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
200 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
211 auto hasTiedInput = [this](const SDNode *N) {
223 SmallPtrSet<SDNode*, 16> Visited
[all...] |
| LegalizeVectorOps.cpp | 78 SDValue TranslateLegalizeResults(SDValue Op, SDNode *Result);
88 bool LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results);
91 SDValue UnrollVSETCC(SDNode *Node);
97 void Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results);
101 void ExpandFP_TO_UINT(SDNode *Node, SmallVectorImpl<SDValue> &Results);
105 void ExpandUINT_TO_FLOAT(SDNode *Node, SmallVectorImpl<SDValue> &Results);
108 SDValue ExpandSEXTINREG(SDNode *Node);
115 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDNode *Node);
122 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDNode *Node);
128 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDNode *Node)
[all...] |
| LegalizeFloatTypes.cpp | 48 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
156 SDValue DAGTypeLegalizer::SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC) {
175 SDValue DAGTypeLegalizer::SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC) {
196 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
200 SDValue DAGTypeLegalizer::SoftenFloatRes_FREEZE(SDNode *N) {
206 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
212 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
221 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) {
245 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
252 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.h | 58 void Select(SDNode *N) override;
59 bool tryIntrinsicNoChain(SDNode *N);
60 bool tryIntrinsicChain(SDNode *N);
61 void SelectTexSurfHandle(SDNode *N);
62 bool tryLoad(SDNode *N);
63 bool tryLoadVector(SDNode *N);
64 bool tryLDGLDU(SDNode *N);
65 bool tryStore(SDNode *N);
66 bool tryStoreVector(SDNode *N);
67 bool tryLoadParam(SDNode *N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.h | 55 void Select(SDNode *N) override;
78 MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
82 SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
84 void SelectFrameIndex(SDNode *N);
91 bool SelectBrevLdIntrinsic(SDNode *IntN);
92 bool SelectNewCircIntrinsic(SDNode *IntN);
93 void SelectLoad(SDNode *N);
96 void SelectStore(SDNode *N);
97 void SelectSHL(SDNode *N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 84 virtual void Select(SDNode *N) = 0;
99 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
105 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
109 static void InvalidateNodeId(SDNode *N);
110 static int getUninvalidatedNodeId(SDNode *N);
112 static void EnforceNodeIdInvariant(SDNode *N);
221 void ReplaceUses(SDNode *F, SDNode *T)
[all...] |
| SelectionDAGNodes.h | 9 // This file declares the SDNode class and derived classes, which are used to
67 class SDNode;
72 void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
91 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
96 bool isConstantSplatVectorAllOnes(const SDNode *N,
102 bool isConstantSplatVectorAllZeros(const SDNode *N,
107 bool isBuildVectorAllOnes(const SDNode *N);
111 bool isBuildVectorAllZeros(const SDNode *N);
115 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
119 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
[all...] |
| SelectionDAG.h | 10 // SDNode class and subclasses.
133 template <> struct ilist_alloc_traits<SDNode> {
134 static void deleteNode(SDNode *) {
135 llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call!");
141 /// instead the info is kept off to the side in this structure. Each SDNode may
155 using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>;
169 void erase(const SDNode *Node);
185 ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) const {
237 SDNode EntryNode;
243 ilist<SDNode> AllNodes
[all...] |
| SelectionDAGAddressAnalysis.h | 80 static bool computeAliasing(const SDNode *Op0,
82 const SDNode *Op1,
87 static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.h | 26 std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
39 bool trySelect(SDNode *Node) override;
|
| MipsISelDAGToDAG.h | 46 SDNode *getGlobalBaseReg();
98 virtual bool selectVSplat(SDNode *N, APInt &Imm,
131 bool selectVecAddAsVecSubIfProfitable(SDNode *Node);
133 void Select(SDNode *N) override;
135 virtual bool trySelect(SDNode *Node) = 0;
138 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
|
| MipsSEISelDAGToDAG.h | 39 std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
43 void selectAddE(SDNode *Node, const SDLoc &DL) const;
96 bool selectVSplat(SDNode *N, APInt &Imm,
129 bool trySelect(SDNode *Node) override;
|
| Mips16ISelDAGToDAG.cpp | 44 std::pair<SDNode *, SDNode *>
45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, const SDLoc &DL, EVT Ty,
47 SDNode *Lo = nullptr, *Hi = nullptr;
48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
179 bool Mips16DAGToDAGISel::trySelect(SDNode *Node) {
198 std::pair<SDNode *, SDNode *> LoHi =
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.h | 41 void Select(SDNode *Node) override;
60 bool MatchSLLIUW(SDNode *N) const;
75 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
81 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
82 void selectVLSEGFF(SDNode *Node, bool IsMasked);
83 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
84 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
85 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.h | 154 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
156 SDValue performUCharToFloatCombine(SDNode *N,
158 SDValue performSHLPtrCombine(SDNode *N,
169 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
170 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
172 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
| AMDGPUISelLowering.h | 75 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
76 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
77 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
85 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
| AMDGPUISelDAGToDAG.cpp | 77 static SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG,
94 static SDNode *packNegConstantV2I16(const SDNode *N, SelectionDAG &DAG) {
128 bool matchLoadD16FromBuildVector(SDNode *N) const;
132 void Select(SDNode *N) override;
137 void SelectBuildVector(SDNode *N, unsigned RegClassID);
142 bool isInlineImmediate(const SDNode *N, bool Negated = false) const;
143 bool isNegInlineImmediate(const SDNode *N) const {
163 bool isVGPRImm(const SDNode *N) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
40 bool selectIndexedLoad(SDNode *N);
50 void Select(SDNode *N) override;
51 bool trySelect(SDNode *N);
53 template <unsigned NodeType> bool select(SDNode *N);
54 bool selectMultiplication(SDNode *N);
64 bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
121 bool AVRDAGToDAGISel::selectIndexedLoad(SDNode *N) {
159 SDNode *ResNode = CurDAG->getMachineNode(Opcode, SDLoc(N), VT,
305 template <> bool AVRDAGToDAGISel::select<ISD::FrameIndex>(SDNode *N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 513 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
515 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
536 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
639 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
640 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
641 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
642 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
644 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
645 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
646 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 429 /// An SDNode for swaps that are not associated with any loads/stores
433 /// An SDNode for Power9 vector absolute value difference.
644 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
665 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
672 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
801 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
839 Sched::Preference getSchedulingPreference(SDNode *N) const override;
848 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
851 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
852 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
