| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUExportClustering.cpp | 69 for (const SDep &Pred : SUb->Preds) {
72 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial));
76 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier));
78 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster));
83 SmallVector<SDep, 2> ToAdd, ToRemove;
85 for (const SDep &Pred : SU.Preds) {
94 for (const SDep &ExportPred : PredSU->Preds)
[all...] |
| SIMachineScheduler.cpp | 424 for (SDep& Succ : SU->Succs) {
434 void SIScheduleBlock::undoReleaseSucc(SUnit *SU, SDep *SuccEdge) {
444 void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) {
465 for (SDep& Succ : SU->Succs) {
497 for (SDep& Succ : SU->Succs) {
648 PredDep.getKind() == llvm::SDep::Data)
801 for (SDep& PredDep : SU->Preds) {
843 for (SDep& SuccDep : SU->Succs) {
927 for (SDep& SuccDep : SU->Succs) {
997 for (SDep& SuccDep : SU->Succs)
[all...] |
| AMDGPUSubtarget.cpp | 814 int UseOpIdx, SDep &Dep) const {
815 if (Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
875 for (const SDep &SI : Succs[I]->Succs) {
888 for (const SDep &SI : SU->Preds)
911 if (SU->addPred(SDep(From, SDep::Artificial), false))
914 for (SDep &SI : From->Succs) {
917 SUv->addPred(SDep(SU, SDep::Artificial), false);
920 for (SDep &SI : SU->Succs)
[all...] |
| GCNILPSched.cpp | 64 for (const SDep &Pred : SU->Preds) {
108 for (const SDep &Succ : SU->Succs) {
123 for (const SDep &Pred : SU->Preds) {
|
| GCNMinRegStrategy.cpp | 88 for (auto SDep : SU->Succs) {
90 for (auto PDep : SDep.getSUnit()->Preds) {
181 S.getKind() != SDep::Data)
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MacroFusion.cpp | 35 static bool isHazard(const SDep &Dep) {
36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output;
40 for (const SDep &SI : SU.Preds)
58 for (SDep &SI : FirstSU.Succs)
62 for (SDep &SI : SecondSU.Preds)
71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster)))
83 for (SDep &SI : FirstSU.Succs)
87 for (SDep &SI : SecondSU.Preds
[all...] |
| ScheduleDAG.cpp | 75 LLVM_DUMP_METHOD void SDep::dump(const TargetRegisterInfo *TRI) const {
107 bool SUnit::addPred(const SDep &D, bool Required) {
109 for (SDep &PredDep : Preds) {
120 SDep ForwardD = PredDep;
122 for (SDep &SuccDep : PredSU->Succs) {
134 SDep P = D;
138 if (D.getKind() == SDep::Data) {
175 void SUnit::removePred(const SDep &D) {
177 SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D);
181 SDep P = D
[all...] |
| ScheduleDAGInstrs.cpp | 256 SDep Dep;
258 Dep = SDep(SU, SDep::Artificial);
263 Dep = SDep(SU, SDep::Data, *Alias);
307 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
316 (Kind != SDep::Output || !MO.isDead() ||
318 SDep Dep(SU, Kind, /*Reg=*/*Alias)
[all...] |
| AggressiveAntiDepBreaker.cpp | 259 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
261 for (const SDep &Pred : SU->Preds) {
262 if ((Pred.getKind() == SDep::Anti) || (Pred.getKind() == SDep::Output)) {
272 const SDep *Next = nullptr;
276 for (const SDep &Pred : SU->Preds) {
283 (NextDepth == PredTotalLatency && Pred.getKind() == SDep::Anti)) {
824 std::vector<const SDep *> Edges;
843 const SDep *Edge = Edges[i];
846 if ((Edge->getKind() != SDep::Anti) &
[all...] |
| MachinePipeliner.cpp | 694 if (SI.getKind() == SDep::Order) {
786 SDep Dep(Load, SDep::Barrier);
796 SDep Dep(Load, SDep::Barrier);
804 SDep Dep(Load, SDep::Barrier);
811 SDep Dep(Load, SDep::Barrier);
820 SDep Dep(Load, SDep::Barrier)
[all...] |
| LatencyPriorityQueue.cpp | 58 for (const SDep &P : SU->Preds) {
92 for (const SDep &Succ : SU->Succs)
|
| CriticalAntiDepBreaker.cpp | 141 static const SDep *CriticalPathStep(const SUnit *SU) {
142 const SDep *Next = nullptr;
145 for (const SDep &P : SU->Preds) {
152 (NextDepth == PredTotalLatency && P.getKind() == SDep::Anti)) {
559 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
563 if (Edge->getKind() == SDep::Anti) {
582 for (const SDep &P : CriticalPathSU->Preds)
584 ? (P.getKind() != SDep::Anti || P.getReg() != AntiDepReg)
585 : (P.getKind() == SDep::Data &&
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 49 class SDep {
99 /// Constructs a null SDep. This is only for use by container classes which
100 /// require default constructors. SUnits may not/ have null SDep edges.
101 SDep() : Dep(nullptr, Data) {}
103 /// Constructs an SDep with the specified values.
104 SDep(SUnit *S, Kind kind, unsigned Reg)
112 "SDep::Anti and SDep::Output must use a non-zero Reg!");
123 SDep(SUnit *S, OrderKind kind)
128 /// Returns true if the specified SDep is equivalent except for latency
[all...] |
| MachinePipeliner.h | 240 bool isBackedge(SUnit *Source, const SDep &Dep) {
241 if (Dep.getKind() != SDep::Anti)
246 bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
250 unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) {
253 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
329 for (const SDep &Succ : Nodes[i]->Succs) {
541 int earliestCycleInChain(const SDep &Dep);
545 int latestCycleInChain(const SDep &Dep);
|
| TargetSubtargetInfo.h | 42 class SDep;
234 int UseOpIdx, SDep &Dep) const {}
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 88 void AddPred(SUnit *SU, const SDep &D) {
94 void RemovePred(SUnit *SU, const SDep &D) {
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
162 for (SDep &Pred : SU->Preds) {
192 for (SDep &Succ : SU->Succs) {
277 SDep ChainPred;
278 SmallVector<SDep, 4> ChainSuccs;
279 SmallVector<SDep, 4> LoadPreds;
280 SmallVector<SDep, 4> NodePreds
[all...] |
| ScheduleDAGRRList.cpp | 225 void AddPredQueued(SUnit *SU, const SDep &D) {
233 void AddPred(SUnit *SU, const SDep &D) {
241 void RemovePred(SUnit *SU, const SDep &D) {
252 void ReleasePred(SUnit *SU, const SDep *PredEdge);
259 void CapturePred(SDep *PredEdge);
398 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
556 for (SDep &Pred : SU->Preds) {
770 for (SDep &Succ : SU->Succs) {
820 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
839 for (SDep &Pred : SU->Preds)
[all...] |
| ScheduleDAGVLIW.cpp | 85 void releaseSucc(SUnit *SU, const SDep &D);
113 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
139 for (SDep &Succ : SU->Succs) {
|
| ResourcePriorityQueue.cpp | 73 for (SDep &Pred : SU->Preds) {
111 for (const SDep &Succ : SU->Succs) {
148 for (const SDep &Succ : SU->Succs)
157 for (SDep &Pred : SU->Preds)
216 for (const SDep &Pred : SU->Preds) {
233 for (const SDep &Succ : SU->Succs)
272 for (const SDep &Succ : Packet[i]->Succs) {
502 for (SDep &Pred : SU->Preds) {
517 for (const SDep &Succ : SU->Succs) {
|
| ScheduleDAGSDNodes.cpp | 507 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
508 : SDep(OpSU, SDep::Data, PhysReg);
647 unsigned OpIdx, SDep& dep) const{
652 if (dep.getKind() != SDep::Data)
811 for (const SDep &Pred : SU->Preds) {
821 for (const SDep &Succ : SU->Succs) {
|
| ScheduleDAGSDNodes.h | 42 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
108 unsigned OpIdx, SDep& dep) const;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 202 SmallVector<SDep, 4> Erase;
204 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
222 for (SDep &SI : SU.Succs) {
223 if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
232 for (SDep &PI : SI.getSUnit()->Preds) {
233 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
281 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
285 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier))
[all...] |
| HexagonVLIWPacketizer.h | 116 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
118 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
126 bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
|
| HexagonVLIWPacketizer.cpp | 305 SDep::Kind DepType, unsigned DepReg) {
319 if (DepType == SDep::Data) {
328 static bool isRegDependence(const SDep::Kind DepType) {
329 return DepType == SDep::Data || DepType == SDep::Anti ||
330 DepType == SDep::Output;
378 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
380 assert(DepType == SDep::Data);
460 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
462 assert(DepType == SDep::Data)
[all...] |
| HexagonSubtarget.h | 37 class SDep;
271 SDep &Dep) const override;
302 void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
|
