| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 28 SELECT_CC,
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| BPFISelLowering.cpp | 120 setOperationAction(ISD::SELECT_CC, VT, Custom);
287 case ISD::SELECT_CC:
621 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
632 case BPFISD::SELECT_CC:
633 return "BPFISD::SELECT_CC";
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 36 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
38 SELECT_CC,
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| LanaiISelLowering.cpp | 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
190 case ISD::SELECT_CC:
998 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1102 case LanaiISD::SELECT_CC:
1103 return "LanaiISD::SELECT_CC";
1499 case LanaiISD::SELECT_CC:
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 684 SELECT_CC,
948 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 73 SELECT_CC
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| AVRISelLowering.cpp | 103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
260 NODE(SELECT_CC);
751 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
768 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
802 case ISD::SELECT_CC:
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| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 62 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
64 SELECT_CC,
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| MSP430ISelLowering.cpp | 96 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
97 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
349 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1212 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1230 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1381 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 133 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
134 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
252 setTargetDAGCombine(ISD::SELECT_CC);
461 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
879 // select_cc f32, f32, -1, 0, cc_supported
880 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
881 // select_cc i32, i32, -1, 0, cc_supported
904 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
911 // select_cc f32, 0.0, f32, f32, cc_supported
912 // select_cc f32, 0.0, i32, i32, cc_supporte
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 129 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
719 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
833 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
1176 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1779 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1803 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2088 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
2156 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
2266 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
2484 // Construct a new SELECT_CC node with the promoted true- and false- values
[all...] |
| LegalizeTypesGeneric.cpp | 553 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
555 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
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| LegalizeDAG.cpp | 1033 case ISD::SELECT_CC:
1038 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1050 if (Node->getOpcode() == ISD::SELECT_CC)
3609 // illegal; expand it into a SELECT_CC.
3621 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3629 case ISD::SELECT_CC: {
3645 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3653 // SELECT_CC is legal, so the condition code must not be.
3682 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3690 // condition code, create a new SELECT_CC node
[all...] |
| LegalizeVectorOps.cpp | 399 case ISD::SELECT_CC:
1382 // illegal; expand it into a SELECT_CC.
1385 DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS,
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| SelectionDAGDumper.cpp | 283 case ISD::SELECT_CC: return "select_cc";
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 115 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
170 assert(LHS.getValueType() == MVT::i32 && "Only know how to SELECT_CC i32");
754 case ISD::SELECT_CC:
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.h | 38 SELECT_CC,
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| RISCVISelLowering.cpp | 175 setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
315 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
327 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
344 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
447 setOperationAction(ISD::SELECT_CC, VT, Expand);
525 setOperationAction(ISD::SELECT_CC, VT, Expand);
582 setOperationAction(ISD::SELECT_CC, VT, Expand);
710 setOperationAction(ISD::SELECT_CC, VT, Expand);
779 setOperationAction(ISD::SELECT_CC, VT, Expand);
2669 // lowered RISCVISD::SELECT_CC to take advantage of the intege
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 455 // PowerPC wants to turn select_cc of FP into fsel when possible.
456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
780 setOperationAction(ISD::SELECT_CC, VT, Promote);
781 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
831 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
1121 // Expand the SELECT to SELECT_CC
1232 // Lower following f128 select_cc pattern:
1233 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, N
[all...] |
| PPCISelDAGToDAG.cpp | 3831 /// the inputs. This can also be used for SELECT_CC if either the true or false
3836 Compare.getOpcode() == ISD::SELECT_CC) &&
3847 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
3848 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
4499 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
4511 // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, cc2)), cc1)
4512 // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, cc2)), cc1)
4513 // (select_cc lhs, rhs, 0, (select_cc [lr]hs, [lr]hs, 1, -1, cc2), seteq
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1414 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1532 // Sparc has no select or setcc: expand to SELECT_CC.
1552 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1553 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1554 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1555 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1572 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
2481 // If this is a select_cc of a "setcc", and if the setcc got lowered into
3036 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
3109 default: llvm_unreachable("Unknown SELECT_CC!");
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 130 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
249 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
253 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
258 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
296 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
1527 assert((MI.getOpcode() == XCore::SELECT_CC) &&
1530 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 854 // bits (as does the pseudo SELECT_CC expansion). I don't think it
2498 case ISD::SELECT_CC:
2528 if (User->getOpcode() == ISD::SELECT_CC ||
2557 if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 196 setOperationAction(ISD::SELECT_CC, T, Expand);
253 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
1955 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I],
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