| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 40 // SETCC - Store the conditional code to a register.
41 SETCC,
|
| LanaiISelLowering.cpp | 88 setOperationAction(ISD::SETCC, MVT::i32, Custom);
192 case ISD::SETCC:
980 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
1104 case LanaiISD::SETCC:
1105 return "LanaiISD::SETCC";
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrInfo.h | 185 static inline bool IsSETCC(unsigned SETCC) {
186 switch (SETCC) {
|
| M68kISelLowering.cpp | 127 setOperationAction(ISD::SETCC, VT, Custom);
164 // M68k SETcc producess either 0x00 or 0xFF
1327 case ISD::SETCC:
1369 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1370 // looks for this combo and may remove the "setcc" instruction if the "setcc"
1402 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1406 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1428 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8
[all...] |
| M68kISelLowering.h | 51 /// M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
53 SETCC,
55 // Same as SETCC except it's materialized with a subx and the value is all
129 /// Return the value type to use for ISD::SETCC.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 2220 { ISD::SETCC, MVT::v2i64, 2 },
2224 { ISD::SETCC, MVT::v32i16, 1 },
2225 { ISD::SETCC, MVT::v64i8, 1 },
2232 { ISD::SETCC, MVT::v8i64, 1 },
2233 { ISD::SETCC, MVT::v16i32, 1 },
2234 { ISD::SETCC, MVT::v8f64, 1 },
2235 { ISD::SETCC, MVT::v16f32, 1 },
2242 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4
2243 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4
2250 { ISD::SETCC, MVT::v4i64, 1 }
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 452 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used
673 /// Much like the scalar select and setcc, each bit in the condition selects
686 /// SetCC operator - This evaluates to a true value iff the condition is
692 SETCC,
694 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
950 /// compare, rather than as a combined SetCC node. The operands in order
1372 /// Return true if this is a setcc instruction that performs a signed
1378 /// Return true if this is a setcc instruction that performs an unsigned
1384 /// Return true if this is a setcc instruction that performs an equality
1403 /// SetCC operation
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 52 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
54 SETCC,
|
| MSP430ISelLowering.cpp | 92 setOperationAction(ISD::SETCC, MVT::i8, Custom);
93 setOperationAction(ISD::SETCC, MVT::i16, Custom);
347 case ISD::SETCC: return LowerSETCC(Op, DAG);
1380 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 498 case ISD::SETCC: {
772 case ISD::SETCC:
1370 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
1371 // condition code, create a new SETCC node.
1373 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC,
1376 // If we expanded the SETCC by inverting the condition code, then wrap
1377 // the existing SETCC in a NOT to restore the intended condition.
1381 // Otherwise, SETCC for the given comparison type must be completely
1529 Ops[i] = DAG.getNode(ISD::SETCC, dl,
|
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
467 if (Cond->getOpcode() == ISD::SETCC) {
574 // Turn it into a scalar SETCC.
575 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
631 case ISD::SETCC:
760 /// result must be v1i1, so just convert to a scalar SETCC and wrap
775 // Turn it into a scalar SETCC.
776 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
944 case ISD::SETCC:
1746 if (Mask.getOpcode() == ISD::SETCC) {
[all...] |
| LegalizeDAG.cpp | 83 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
84 /// will attempt merge setcc and brc instructions into brcc's.
1036 case ISD::SETCC:
1041 Node->getOpcode() == ISD::SETCC ? 2 : 1;
3490 if (Tmp1.getOpcode() == ISD::SETCC) {
3545 // Expand brcond's setcc into its constituent parts and create a BR_CC
3549 if (Tmp2.getOpcode() == ISD::SETCC) {
3571 case ISD::SETCC:
3574 bool IsStrict = Node->getOpcode() != ISD::SETCC;
3586 // If we expanded the SETCC by swapping LHS and RHS, or by inverting th
[all...] |
| DAGCombiner.cpp | 887 // Return true if this node is a setcc, or is a select_cc
889 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
894 if (N.getOpcode() == ISD::SETCC) {
925 /// Return true if this is a SetCC-equivalent operation with only one use.
1667 case ISD::SETCC: return visitSETCC(N);
2182 // Match the zext operand as a setcc of a boolean.
2183 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2187 // Match the compare as: setcc (X & 1), 0, eq.
2188 SDValue SetCC = Z.getOperand(0);
2189 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get()
[all...] |
| LegalizeTypesGeneric.cpp | 527 else if (Cond.getOpcode() == ISD::SETCC) {
528 // If the condition is a vXi1 vector, and the LHS of the setcc is a legal
529 // type and the setcc result type is the same vXi1, then leave the setcc
|
| SelectionDAGDumper.cpp | 277 case ISD::SETCC: return "setcc";
437 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeFloatTypes.cpp | 836 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
1017 NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS,
1026 "Unexpected setcc expansion!");
1782 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1803 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1813 assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
1957 "Unexpected setcc expansion!");
2089 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
2161 // Construct a SETCC that compares the promoted values and sets the conditional
2886 case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 183 setOperationAction(ISD::SETCC, T, Custom);
212 setOperationAction(ISD::SETCC, BoolW, Custom);
256 setOperationAction(ISD::SETCC, VecTy, Custom);
264 setOperationAction(ISD::SETCC, BoolTy, Custom);
1964 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy,
1969 {SetCC, getZero(dl, MVT::i32, DAG)});
2087 case ISD::SETCC:
2118 case ISD::SETCC:
2147 case ISD::SETCC
[all...] |
| HexagonISelLowering.cpp | 1519 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1520 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1521 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1522 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1748 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
3168 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 107 setOperationAction(ISD::SETCC, MVT::i8, Custom);
108 setOperationAction(ISD::SETCC, MVT::i16, Custom);
109 setOperationAction(ISD::SETCC, MVT::i32, Custom);
110 setOperationAction(ISD::SETCC, MVT::i64, Custom);
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
804 case ISD::SETCC:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 105 setTargetDAGCombine(ISD::SETCC);
128 setOperationAction(ISD::SETCC, MVT::f16, Promote);
247 setOperationAction(ISD::SETCC, MVT::i32, Legal);
251 setOperationAction(ISD::SETCC, MVT::f32, Legal);
256 setOperationAction(ISD::SETCC, MVT::f64, Legal);
294 setOperationAction(ISD::SETCC, MVT::i64, Legal);
362 setOperationAction(ISD::SETCC, Ty, Legal);
399 setOperationAction(ISD::SETCC, Ty, Legal);
985 SDValue SetCC = N->getOperand(0);
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.h | 367 // This is SETCC with the full mask result which is used for a compare with a
369 SETCC,
|
| R600ISelLowering.cpp | 119 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
120 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
136 setOperationAction(ISD::SETCC, MVT::i32, Expand);
137 setOperationAction(ISD::SETCC, MVT::f32, Expand);
796 ISD::SETCC,
806 ISD::SETCC,
|
| SIISelLowering.cpp | 198 setOperationAction(ISD::SETCC, MVT::i1, Promote);
199 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
200 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
201 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
812 setTargetDAGCombine(ISD::SETCC);
1602 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1603 if (VT == MVT::i1 && Op == ISD::SETCC)
4704 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 118 setOperationAction(ISD::SETCC, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1532 // Sparc has no select or setcc: expand to SELECT_CC.
1538 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1539 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1540 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1541 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1570 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1887 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1888 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2444 // If this is a br_cc of a "setcc", and if the setcc got lowered int
[all...] |
