| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1336 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1361 SETEQ, // 1 X 0 0 1 True if equal
1387 return Code == SETEQ || Code == SETNE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelDAGToDAG.cpp | 31 case ISD::SETEQ:
61 case ISD::SETEQ:
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 320 case ISD::SETEQ:
3152 (Cond != ISD::SETEQ && Cond != ISD::SETNE))
3236 NewCond = ISD::CondCode::SETEQ;
3238 NewCond = ISD::CondCode::SETEQ;
3305 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3378 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode");
3451 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
3456 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) {
3473 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3530 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &
[all...] |
| LegalizeIntegerTypes.cpp | 1595 case ISD::SETEQ:
2137 N->getOperand(2), ISD::SETEQ);
2447 ISD::SETEQ);
2540 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
3566 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3572 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3579 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3585 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
4245 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
4374 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
[all...] |
| SelectionDAGDumper.cpp | 454 case ISD::SETEQ: return "seteq";
|
| LegalizeDAG.cpp | 2809 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
3438 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3439 : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3728 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE);
|
| SelectionDAGBuilder.cpp | 2174 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2329 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2370 // C = seteq
2425 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2460 CB.CC == ISD::SETEQ)
2463 CB.CC == ISD::SETEQ) {
2824 ISD::SETEQ);
10521 ISD::SETEQ);
10685 CC = ISD::SETEQ;
|
| DAGCombiner.cpp | 2190 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2197 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2198 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
4137 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4230 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
4231 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
4278 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4374 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4978 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4986 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 3157 case ISD::SETEQ: {
3158 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
3159 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
3331 case ISD::SETEQ: {
3332 // (sext (setcc %a, %b, seteq)) ->
3334 // (sext (setcc %a, 0, seteq)) ->
3502 case ISD::SETEQ: {
3503 // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
3504 // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
3659 case ISD::SETEQ:
[all...] |
| PPCISelLowering.cpp | 3472 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3501 // If we have an integer seteq/setne, turn it into a compare against zero
3506 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7846 case ISD::SETEQ:
7881 case ISD::SETEQ:
13559 if (CC == ISD::SETNE || CC == ISD::SETEQ) {
15304 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
15308 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
15325 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
15333 if (CC == ISD::SETEQ) // Cond never true, remove branch
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| Analysis.cpp | 214 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ;
229 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
|
| TargetLoweringBase.cpp | 641 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
642 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
643 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
644 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1427 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
1485 case ISD::SETEQ:
1564 case ISD::SETEQ:
1915 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1926 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1945 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2252 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 1396 case ISD::SETEQ:
1888 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1910 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1944 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1948 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
2357 SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2380 SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2386 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2464 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2657 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
[all...] |
| R600ISelLowering.cpp | 800 DAG.getCondCode(ISD::SETEQ));
810 DAG.getCondCode(ISD::SETEQ));
1876 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1900 case ISD::SETEQ: {
|
| SIISelLowering.cpp | 6701 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
8581 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
8582 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
10201 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ);
10266 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ);
10687 (CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
10691 (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
10698 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10712 if ((CF == CRHSVal && CC == ISD::SETEQ) ||
10717 (CT == CRHSVal && CC == ISD::SETEQ))
[all...] |
| SIWholeQuadMode.cpp | 828 case ISD::SETEQ:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
810 case ISD::SETEQ:
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1316 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | 1004 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1021 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1029 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1076 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
|
| X86ISelLowering.cpp | 5012 case ISD::SETEQ: return X86::COND_E;
5084 case ISD::SETEQ: return X86::COND_E;
10099 ISD::CondCode::SETEQ);
18928 ISD::CondCode::SETEQ);
22112 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode");
22113 X86CC = (CC == ISD::SETEQ ? X86::COND_E : X86::COND_NE);
22171 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode");
22687 X86CC = DAG.getTargetConstant(CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B,
22711 case ISD::SETEQ: SSECC = 0; break;
22738 case ISD::SETEQ
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 199 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
205 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
1049 case ISD::SETEQ:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 54 case ISD::SETEQ:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 790 SET_NEWCC(SETEQ, JEQ);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 954 case ISD::SETEQ:
1718 Op->getOperand(2), ISD::SETEQ);
1724 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 568 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
585 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
1939 case ISD::SETEQ: return ARMCC::EQ;
1957 case ISD::SETEQ:
3919 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3921 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
5403 CC = ISD::SETEQ;
5501 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5533 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
6459 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE))
[all...] |
