| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1336 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1364 SETLT, // 1 X 1 0 0 True if less than
1375 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelDAGToDAG.cpp | 35 case ISD::SETLT:
67 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 583 case ISD::SETLT:
792 SET_NEWCC(SETLT, JSLT);
803 CC == ISD::SETLT ||
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| Analysis.cpp | 216 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;
235 case ICmpInst::ICMP_SLT: return ISD::SETLT;
|
| TargetLoweringBase.cpp | 653 CCs[RTLIB::OLT_F32] = ISD::SETLT;
654 CCs[RTLIB::OLT_F64] = ISD::SETLT;
655 CCs[RTLIB::OLT_F128] = ISD::SETLT;
656 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 3224 // Handle SETLT -1 (which is equivalent to SETGE 0).
3247 case ISD::SETLT: {
3248 // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
3249 // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1)
3250 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31)
3251 // Handle SETLT 1 (which is equivalent to SETLE 0).
3426 case ISD::SETLT: {
3581 case ISD::SETLT: {
3583 // (zext (setcc %a, %b, setlt)) ->
3585 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 338 case ISD::SETLT:
784 // if we don't care about FP signed-zero. The use of SETLT with FP means
786 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
1426 // if we don't care about FP signed-zero. The use of SETLT with FP means
1428 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
3721 case ISD::SETLT:
3929 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3941 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3947 // Canonicalize setlt X, Max --> setne X, Max
4050 // SETUGT X, SINTMAX -> SETLT X,
[all...] |
| LegalizeIntegerTypes.cpp | 1627 case ISD::SETLT:
2512 return std::make_pair(ISD::SETLT, ISD::UMIN);
3430 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
3571 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3580 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3584 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3598 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3693 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
4268 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
4279 case ISD::SETLT
[all...] |
| SelectionDAGDumper.cpp | 457 case ISD::SETLT: return "setlt";
|
| LegalizeDAG.cpp | 2397 dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2453 DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
3138 case ISD::SMIN: Pred = ISD::SETLT; break;
|
| DAGCombiner.cpp | 4241 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
4984 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4989 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4999 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
5006 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
9185 case ISD::SETLT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 505 case ISD::SETLT:
577 CC = ISD::SETLT;
592 CC = ISD::SETLT;
595 case ISD::SETLT: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | 1008 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1025 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1033 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1080 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
|
| X86ISelLowering.cpp | 983 setCondCodeAction(ISD::SETLT, VT, Custom);
1319 setCondCodeAction(ISD::SETLT, VT, Custom);
1660 setCondCodeAction(ISD::SETLT, VT, Custom);
5015 case ISD::SETLT: return X86::COND_L;
5038 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
5046 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
5093 case ISD::SETLT: return X86::COND_B;
19921 SDValue IsNeg = DAG.getSetCC(DL, MVT::v4i64, Src, Zero, ISD::SETLT);
20541 Op.getOperand(OpNo), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
22590 SDValue Cmp = DAG.getSetCC(DL, MVT::i8, N0, Zero, ISD::SETLT);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
1108 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 60 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1491 case ISD::SETLT:
1521 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1525 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1576 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 1413 case ISD::SETLT: {
2070 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
2071 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
2192 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2685 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
|
| SIWholeQuadMode.cpp | 840 case ISD::SETLT:
|
| R600ISelLowering.cpp | 100 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
112 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 956 case ISD::SETLT:
1754 Op->getOperand(2), ISD::SETLT);
1760 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
822 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1942 case ISD::SETLT: return ARMCC::LT;
1971 case ISD::SETLT:
4504 case ISD::SETLT:
4507 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4521 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4937 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4943 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5008 return CC == ISD::SETLT || CC == ISD::SETLE;
6494 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
6541 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1369 case ISD::SETLT: return SPCC::ICC_L;
1389 case ISD::SETLT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 338 setCondCodeAction(ISD::SETLT, VT, Expand);
1446 setCondCodeAction(ISD::SETLT, VT, Expand);
2235 case ISD::SETLT:
2296 case ISD::SETLT:
2796 case ISD::SETLT:
2802 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2823 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
6675 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
12018 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
14120 return tryConvertSVEWideCompare(N, ISD::SETLT, DCI, DAG)
[all...] |
