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    Searched refs:SETOGT (Results 1 - 24 of 24) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1345 SETOGT, // 0 0 1 0 True if ordered and greater than
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelDAGToDAG.cpp 71 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
Analysis.cpp 194 case FCmpInst::FCMP_OGT: return ISD::SETOGT;
218 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 439 case ISD::SETOGT: return "setogt";
TargetLowering.cpp 351 case ISD::SETOGT:
4193 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break;
8697 ISD::CondCode::SETOGT);
8847 // SETOGT || SETOLT, inverting the result for SETUEQ. We only need one
8848 // of SETOGT/SETOLT to be legal, the other can be emulated by swapping
8852 (TLI.isCondCodeLegal(ISD::SETOGT, OpVT) ||
8854 CC1 = ISD::SETOGT;
8862 case ISD::SETOGT:
SelectionDAG.cpp 543 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
2223 case ISD::SETOGT:
2303 case ISD::SETOGT: return getBoolConstant(R==APFloat::cmpGreaterThan, dl,
DAGCombiner.cpp 9201 case ISD::SETOGT:
13825 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 4054 case ISD::SETOGT:
4081 case ISD::SETOGT:
4127 case ISD::SETOGT:
4150 case ISD::SETOGT:
4151 case ISD::SETGT: return 1; // Bit #1 = SETOGT
4188 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
4197 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
4211 case ISD::SETOGT:
PPCISelLowering.cpp 7820 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 264 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
269 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
401 setCondCodeAction(ISD::SETOGT, Ty, Expand);
MipsISelLowering.cpp 611 case ISD::SETOGT: return Mips::FCOND_OGT;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIWholeQuadMode.cpp 831 case ISD::SETOGT:
AMDGPUISelLowering.cpp 1438 case ISD::SETOGT: {
2128 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2223 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
SIISelLowering.cpp 8383 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 855 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 2105 ISD::SETOGT);
2148 ISD::SETOGT);
NVPTXISelDAGToDAG.cpp 545 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 1567 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 2738 case ISD::SETOGT:
2858 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
2875 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
2877 SDValue GT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1392 case ISD::SETOGT: return SPCC::FCC_G;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 299 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
548 ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1960 case ISD::SETOGT: CondCode = ARMCC::GT; break;
4936 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
6495 case ISD::SETOGT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 5086 case ISD::SETOGT:
21663 dl, Src, MaxFloatNode, MaxIntNode, Select, ISD::CondCode::SETOGT);
22712 case ISD::SETOGT:
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 2263 case ISD::SETOGT:

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