HomeSort by: relevance | last modified time | path
    Searched refs:SETUGE (Results 1 - 25 of 33) sorted by relevancy

1 2

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1337 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1354 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
1381 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelDAGToDAG.cpp 49 case ISD::SETUGE:
93 case ISD::SETUGE:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
Analysis.cpp 203 case FCmpInst::FCMP_UGE: return ISD::SETUGE;
219 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
234 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 1429 case ISD::SETUGE:
1885 ISD::SETUGE);
1887 ISD::SETUGE);
1907 ISD::SETUGE);
1909 ISD::SETUGE);
1967 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1973 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
2021 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE);
2028 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE);
SIWholeQuadMode.cpp 809 case ISD::SETUGE:
R600ISelLowering.cpp 106 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 507 case ISD::SETUGE:
620 CC = ISD::SETUGE;
628 CC = ISD::SETUGE;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 449 case ISD::SETUGE: return "setuge";
TargetLowering.cpp 395 case ISD::SETUGE:
3245 } else if (Cond == ISD::CondCode::SETUGE) {
3710 case ISD::SETUGE:
3735 case ISD::SETUGE:
3901 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
4051 // SETUGE X, SINTMIN -> SETLT X, 0
4053 (Cond == ISD::SETUGE && C1.isMinSignedValue()))
4129 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
4142 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4191 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break
    [all...]
LegalizeIntegerTypes.cpp 1618 case ISD::SETUGE:
4286 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4318 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
4352 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
DAGCombiner.cpp 5017 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
5026 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
9206 case ISD::SETUGE: {
9953 if (SatCC == ISD::SETUGE) {
10005 if (SatCC == ISD::SETUGE || SatCC == ISD::SETUGT)
10014 if ((SatCC == ISD::SETUGE || SatCC == ISD::SETUGT) &&
13828 case ISD::SETUGE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 46 case ISD::SETUGE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 789 SET_NEWCC(SETUGE, JUGE);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 3276 case ISD::SETUGE:
3277 // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
3449 case ISD::SETUGE:
3450 // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
3608 case ISD::SETUGE:
3610 // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
3771 case ISD::SETUGE:
3773 // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
4049 case ISD::SETUGE:
4076 case ISD::SETUGE
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 265 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
366 setCondCodeAction(ISD::SETUGE, Ty, Expand);
402 setCondCodeAction(ISD::SETUGE, Ty, Expand);
963 case ISD::SETUGE: return !IsV216;
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 1499 case ISD::SETUGE:
1549 case ISD::SETUGE:
1578 case ISD::SETUGE: // flipped
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 806 // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
846 case ISD::SETUGE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 105 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
216 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 1066 case ISD::SETUGE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1376 case ISD::SETUGE: return SPCC::ICC_CC;
1400 case ISD::SETUGE: return SPCC::FCC_UGE;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 343 setCondCodeAction(ISD::SETUGE, VT, Expand);
1451 setCondCodeAction(ISD::SETUGE, VT, Expand);
2241 case ISD::SETUGE:
2293 case ISD::SETUGE:
2365 case ISD::SETUGE:
2808 case ISD::SETUGE:
2834 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
14064 N->getOperand(3), DAG.getCondCode(ISD::SETUGE));
14124 return tryConvertSVEWideCompare(N, ISD::SETUGE, DCI, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1945 case ISD::SETUGE: return ARMCC::HS;
1970 case ISD::SETUGE: CondCode = ARMCC::PL; break;
4512 case ISD::SETUGE:
4528 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4931 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4954 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
6501 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH;
6548 case ISD::SETUGE: Opc = ARMCC::HS; break;
16626 (CC == ISD::SETUGE && Imm == 1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 144 setCondCodeAction(ISD::SETUGE, T, Expand);
HexagonISelLowering.cpp 1742 setCondCodeAction(ISD::SETUGE, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 563 case ISD::SETUGE:

Completed in 287 milliseconds

1 2