| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1337 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1356 SETULE, // 1 1 0 1 True if unordered, less than, or equal
1381 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelDAGToDAG.cpp | 45 case ISD::SETULE:
91 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| Analysis.cpp | 205 case FCmpInst::FCMP_ULE: return ISD::SETULE;
217 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE;
232 case ICmpInst::ICMP_ULE: return ISD::SETULE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 582 case ISD::SETULE:
795 SET_NEWCC(SETULE, JULE);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 3278 // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
3281 case ISD::SETULE: {
3451 // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
3454 case ISD::SETULE: {
3613 case ISD::SETULE: {
3615 // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
3776 case ISD::SETULE: {
3778 // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
4057 case ISD::SETULE:
4084 case ISD::SETULE
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 451 case ISD::SETULE: return "setule";
|
| TargetLowering.cpp | 385 case ISD::SETULE:
3237 } else if (Cond == ISD::CondCode::SETULE) {
3714 case ISD::SETULE:
3737 case ISD::SETULE: {
3921 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
4059 // SETULE X, SINTMAX -> SETGT X, -1
4061 (Cond == ISD::SETULE && C1.isMaxSignedValue()))
4130 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
4131 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
4142 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE
[all...] |
| LegalizeIntegerTypes.cpp | 1620 case ISD::SETULE:
4284 case ISD::SETULE: LowCC = ISD::SETULE; break;
4318 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
4352 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
|
| SelectionDAG.cpp | 498 case ISD::SETULE:
541 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
2267 case ISD::SETULE: return getBoolConstant(C1.ule(C2), dl, VT, OpVT);
2331 case ISD::SETULE: return getBoolConstant(R!=APFloat::cmpGreaterThan, dl,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 50 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 961 case ISD::SETULE:
1742 Op->getOperand(2), ISD::SETULE);
1748 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1851 Op->getOperand(2), ISD::SETULE);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIWholeQuadMode.cpp | 815 case ISD::SETULE:
|
| R600ISelLowering.cpp | 109 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
113 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 806 // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
838 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1503 case ISD::SETULE:
1579 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 105 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
216 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 617 case ISD::SETULE: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1063 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1374 case ISD::SETULE: return SPCC::ICC_LEU;
1398 case ISD::SETULE: return SPCC::FCC_ULE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1947 case ISD::SETULE: return ARMCC::LS;
1974 case ISD::SETULE: CondCode = ARMCC::LE; break;
4514 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4525 case ISD::SETULE:
4528 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4932 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4942 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4954 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
6502 case ISD::SETULE: Invert = true; Opc = ARMCC::GT; break;
6547 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 342 setCondCodeAction(ISD::SETULE, VT, Expand);
1450 setCondCodeAction(ISD::SETULE, VT, Expand);
2245 case ISD::SETULE:
2301 case ISD::SETULE:
2363 case ISD::SETULE:
2812 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2828 case ISD::SETULE:
2834 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
14130 return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 143 setCondCodeAction(ISD::SETULE, T, Expand);
|
| HexagonISelLowering.cpp | 1741 setCondCodeAction(ISD::SETULE, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 567 case ISD::SETULE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 300 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
547 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO,
1009 case ISD::SETULE:
|
