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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1315 /// SEXTLOAD loads the integer operand and sign extends it to a larger
1321 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD };
BasicTTIImpl.h 905 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
SelectionDAGNodes.h 2684 /// Returns true if the specified node is a SEXTLOAD.
2687 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 143 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 695 case ISD::SEXTLOAD: OS << ", sext"; break;
727 case ISD::SEXTLOAD: OS << ", sext"; break;
764 case ISD::SEXTLOAD: OS << ", sext"; break;
DAGCombiner.cpp 5881 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
9917 auto LoadExtOpcode = IsSigned ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
10190 // Now LoadExt is either SEXTLOAD or ZEXTLOAD, ExtOpcode must have the same
10192 if ((LoadExt == ISD::SEXTLOAD && ExtOpcode != ISD::SIGN_EXTEND) ||
10200 /// (sext (select c, load x, load y)) -> (select c, sextload x, sextload y)
10227 ExtLoadOpcode = ISD::SEXTLOAD;
10430 // (v8i32 (concat_vectors (v4i32 (sextload x)),
10431 // (v4i32 (sextload (x + 16)))))
10436 // (v8i32 (concat_vectors (v4i32 (sextload x))
    [all...]
LegalizeDAG.cpp 757 if (ExtType == ISD::SEXTLOAD)
930 if (ExtType == ISD::SEXTLOAD)
3529 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 51 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
52 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
53 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
66 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1336 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1414 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1523 // isn't expected here. It attempts to create this sextload, but it ends up
1534 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1535 Ext = ISD::SEXTLOAD;
    [all...]
AMDGPUISelLowering.cpp 124 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
132 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
133 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
150 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
153 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
162 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand)
    [all...]
AMDGPUISelDAGToDAG.cpp 418 // build_vector lo, (sextload ptr from i8) -> load_d16_hi_i8 ptr, lo
432 LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ?
450 // build_vector (sextload ptr from i8), hi -> load_d16_lo_i8 ptr, hi
460 LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ?
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1602 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1663 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1682 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1685 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
HexagonISelDAGToDAG.cpp 138 if (ExtType == ISD::SEXTLOAD)
292 IntExt = ISD::SEXTLOAD;
1475 if (L->getExtensionType() != ISD::SEXTLOAD)
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 881 // Sign : ISD::SEXTLOAD
899 if (PlainLoad && (PlainLoad->getExtensionType() == ISD::SEXTLOAD))
1027 // Sign : ISD::SEXTLOAD
1038 if (ExtensionType == ISD::SEXTLOAD)
1681 bool IsSigned = LdNode->getExtensionType() == ISD::SEXTLOAD;
NVPTXISelLowering.cpp 454 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
4491 if (ExtType == ISD::SEXTLOAD) {
4492 // If for some reason the load is a sextload, the and is needed to zero
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 267 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
275 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
281 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 1601 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1605 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1687 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1752 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1768 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1442 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1446 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1477 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1289 else if (ExtType == ISD::SEXTLOAD)
1299 if (ExtType == ISD::SEXTLOAD) {
1312 if (ExtType == ISD::SEXTLOAD) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 315 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
489 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
2703 // (set dst, (i64 (sextload baseptr))) or
2708 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 2991 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
3030 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
5139 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
5176 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 299 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
333 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
2097 if (Load->getExtensionType() == ISD::SEXTLOAD) {
2130 ISD::SEXTLOAD :
2160 case ISD::SEXTLOAD:
2313 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {

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