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  /src/external/apache2/llvm/dist/llvm/lib/IR/
ReplaceConstant.cpp 53 case Instruction::SExt:
Instructions.cpp 2653 case Instruction::SExt:
2696 case Instruction::SExt:
2744 // SEXT < Integral Signed Integer Any
2761 // and causes issues when building libgcc. We disallow fptosi+sext for the
2773 { 8, 0, 1,99,99, 0, 2,99,99,99, 0, 3, 0}, // SExt |
2871 // zext, sext -> zext, because sext can't sign extend after zext
2953 case SExt: return new SExtInst (S, Ty, Name, InsertBefore);
2975 case SExt: return new SExtInst (S, Ty, Name, InsertAtEnd);
3011 return Create(Instruction::SExt, S, Ty, Name, InsertBefore)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.h 62 enum { SExt, ZExt };
HexagonOptimizeSZextends.cpp 75 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) {
97 // Try to remove redundant sext operations on Hexagon. The hardware
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/AggressiveInstCombine/
TruncInstCombine.cpp 17 // The only exception is for {ZExt, SExt}Inst with operand type equal to
54 case Instruction::SExt:
118 case Instruction::SExt:
324 case Instruction::SExt: {
337 Opc == Instruction::SExt);
398 // it, because {SExt, ZExt}Inst Instruction might have other users that was
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LowerExpectIntrinsic.cpp 145 if (SExtInst *SExt = dyn_cast<SExtInst>(V)) {
146 V = SExt->getOperand(0);
147 Operations.push_back(SExt);
174 case Instruction::SExt:
175 Result = Result.sext(Op->getType()->getIntegerBitWidth());
SpeculativeExecution.cpp 228 case Instruction::SExt:
NaryReassociate.cpp 244 // I = &a[sext(i +nsw j)] // assuming sizeof(a[0]) = 4
246 // NewI = &a[sext(i)] + sext(j).
249 // getSCEV(I) = a + 4 * sext(i + j)
250 // getSCEV(newI) = a + 4 * sext(i) + 4 * sext(j)
359 if (SExtInst *SExt = dyn_cast<SExtInst>(IndexToSplit)) {
360 IndexToSplit = SExt->getOperand(0);
362 // zext can be treated as sext if the source is non-negative.
368 // If the I-th index needs sext and the underlying add is not equipped wit
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
TargetLibraryInfo.h 373 return Signed ? Attribute::SExt : Attribute::ZExt;
375 return Attribute::SExt;
384 return Signed ? Attribute::SExt : Attribute::ZExt;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMParallelDSP.cpp 104 if (auto *SExt = dyn_cast<SExtInst>(V)) {
105 if (auto *I = dyn_cast<Instruction>(SExt->getOperand(0)))
336 if (auto *SExt = dyn_cast<SExtInst>(V)) {
337 if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
340 if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) {
477 case Instruction::SExt:
490 // sext0 = sext i16 %ld0 to i32
492 // sext1 = sext i16 %ld1 to i32
495 // sext2 = sext i16 %ld2 to i32
497 // sext3 = sext i16 %ld3 to i3
    [all...]
MVELaneInterleavingPass.cpp 9 // This pass interleaves around sext/zext/trunc instructions. MVE does not have
10 // a single sext/zext or trunc instruction that takes the bottom half of a
16 // instruction, we often have to turn sext/zext/trunc into a series of lane
20 // blobs of operations that end with sext/zext (or constants/splats) of the
22 // %sa = sext v8i16 %a to v8i32
23 // %sb = sext v8i16 %b to v8i32
28 // %sa = sext v8i16 %sha to v8i32
30 // %sb = sext v8i16 %shb to v8i32
186 case Instruction::SExt:
341 bool Sext = isa<SExtInst>(I)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
Analysis.cpp 578 } else if (CallerAttrs.contains(Attribute::SExt)) {
579 if (!CalleeAttrs.contains(Attribute::SExt))
583 CallerAttrs.removeAttribute(Attribute::SExt);
584 CalleeAttrs.removeAttribute(Attribute::SExt);
587 // Drop sext and zext return attributes if the result is not used.
598 CalleeAttrs.removeAttribute(Attribute::SExt);
InterleavedLoadCombinePass.cpp 170 SExt,
504 A = A.sext(n);
505 pushBOperation(SExt, APInt(sizeof(n) * 8, n));
593 case SExt:
594 OS << "SExt ";
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CallingConvLower.h 37 SExt, // The value is sign extended in the location.
157 return (HTP == AExt || HTP == SExt || HTP == ZExt);
FastISel.h 113 RetSExt = Call.hasRetAttr(Attribute::SExt);
137 RetSExt = Call.hasRetAttr(Attribute::SExt);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineNegator.cpp 208 case Instruction::SExt:
212 return I->getOpcode() == Instruction::SExt
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFAdjustOpt.cpp 284 // ZEXT/SEXT which is used for GEP.
286 Inst->getOpcode() == Instruction::SExt) {
BPFISelLowering.cpp 339 if (VA.getLocInfo() == CCValAssign::SExt)
429 case CCValAssign::SExt:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 156 case CCValAssign::LocInfo::SExt:
193 if (VA.getLocInfo() == CCValAssign::SExt ||
295 case CCValAssign::SExt: {
354 return CCValAssign::LocInfo::SExt;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 171 case Instruction::SExt:
676 // cost for a Select / ZExt or SExt instruction.
744 if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
752 if (Opcode == Instruction::SExt)
781 if (Opcode == Instruction::ZExt || Opcode == Instruction::SExt) {
783 // ZExt/SExt will be handled with one unpack per doubling of width.
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 841 if (Attrs.hasParamAttribute(I, Attribute::SExt))
1008 const auto *SExt = cast<SExtInst>(I);
1010 const Value *Op = SExt->getOperand(0);
1012 MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
1020 updateValueMap(SExt, Reg);
1370 if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
1404 case Instruction::SExt:
  /src/external/apache2/llvm/dist/clang/include/clang/CodeGen/
CGFunctionInfo.h 332 void setSignExt(bool SExt) {
334 SignExt = SExt;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 37 if (AttrFn(Attribute::SExt))
1078 case CCValAssign::SExt: {
1104 case CCValAssign::LocInfo::SExt: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURewriteOutArguments.cpp 357 RetAttrs.addAttribute(Attribute::SExt);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86PartialReduction.cpp 86 // used twice. Only check this when SSE4.1 is enabled and we have zext/sext
105 (Cast->getOpcode() == Instruction::SExt ||

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