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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.h 51 #define SF(reg_name, field_name, post_fix)\
89 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
91 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
92 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
93 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
94 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
95 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
96 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
97 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),
    [all...]
dcn10_optc.h 178 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
179 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
180 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
181 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
182 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
183 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
184 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
185 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
186 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
187 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),
    [all...]
dcn10_mpc.h 63 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
64 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
65 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
71 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),
    [all...]
amdgpu_dcn10_resource.c 272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_dwb.h 55 #define SF(reg_name, field_name, post_fix)\
108 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
111 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
115 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
116 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),
    [all...]
dcn20_optc.h 50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
55 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),
    [all...]
dcn20_mmhubbub.h 57 #define SF(reg_name, field_name, post_fix)\
120 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
122 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
123 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
125 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
126 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
127 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
128 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),
    [all...]
dcn20_vmid.h 43 #define SF(reg_name, field_name, post_fix)\
56 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
57 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
58 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
59 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
60 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
61 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
62 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
63 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
dcn20_mpc.h 140 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
141 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
142 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
143 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
144 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
145 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
146 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
147 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
148 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
149 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_audio.h 46 #define SF(reg_name, field_name, post_fix)\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
55 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
56 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
58 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
59 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),
    [all...]
dce_mem_input.h 185 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
186 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
231 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
232 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
233 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
234 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
235 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
239 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
dce_hwseq.h 449 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
493 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
501 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
502 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
503 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
504 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
505 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
  /src/sys/external/bsd/compiler_rt/dist/lib/fuzzer/
FuzzerDataFlowTrace.cpp 45 for (auto &SF : Files) {
46 auto Name = Basename(SF.File);
54 std::ifstream IF(SF.File);
FuzzerMerge.cpp 269 for (auto &SF: AllFiles)
270 ControlFile << SF.File << "\n";
FuzzerLoop.cpp 780 for (auto &SF : SizedFiles) {
781 auto U = FileToVector(SF.File, MaxInputLen, /*ExitOnError=*/false);
  /src/sys/arch/sh3/sh3/
db_interface.c 584 struct switchframe *sf = &curpcb->pcb_sf; local in function:db_frame_cmd
590 #define SF(x) db_printf("sf_" #x "\t\t0x%08x\t", sf->sf_ ## x); \
591 __db_print_symbol(sf->sf_ ## x)
593 SF(sr);
594 SF(pr);
595 SF(gbr);
596 SF(r8);
597 SF(r9);
598 SF(r10)
    [all...]
  /src/usr.sbin/lpr/common_source/
lp.h 72 extern long SF; /* suppress FF on each print job */
common.c 103 long SF; /* suppress FF on each print job */
  /src/bin/pax/
options.h 70 #define SF 0x000001000ULL
options.c 447 flg |= SF;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 74 #define SF(reg_name, field_name, post_fix)\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 72 #define SF(reg_name, field_name, post_fix)\
  /src/usr.sbin/lpr/lpd/
printjob.c 311 if (!SF && !tof)
560 if (!SF && !tof) { /* start on a fresh page */
1018 if (!SF && !tof)
1046 if (!SF)
1299 SF = (cgetcap(bp, "sf", ':') != NULL);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 360 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
361 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 401 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
402 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\

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