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    Searched refs:SHL_PARTS (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 702 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
705 SHL_PARTS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 121 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
194 case ISD::SHL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 311 case ISD::SHL_PARTS: return "shl_parts";
LegalizeDAG.cpp 1223 case ISD::SHL_PARTS: {
LegalizeIntegerTypes.cpp 3746 PartsOpc = ISD::SHL_PARTS;
3754 // Next check to see if the target supports this SHL_PARTS operation or if it
3755 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3771 // the new SHL_PARTS operation would need further legalization.
SelectionDAG.cpp 7986 case ISD::SHL_PARTS:
TargetLowering.cpp 6610 bool IsSHL = Node->getOpcode() == ISD::SHL_PARTS;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 113 setOperationAction(ISD::SHL_PARTS, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 111 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
112 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 395 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
398 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
2000 /// LowerShiftLeftParts - Lower SHL_PARTS, which
2008 assert(Op.getOpcode() == ISD::SHL_PARTS);
2177 case ISD::SHL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 193 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
454 case ISD::SHL_PARTS:
SIISelLowering.cpp 234 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 375 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1226 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 101 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1652 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1686 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 165 // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
166 setOperationAction(ISD::SHL_PARTS, IntVT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 129 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1586 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 688 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
693 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
10825 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1144 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
6056 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
6070 assert(Op.getOpcode() == ISD::SHL_PARTS);
9881 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 236 setOperationAction(ISD::SHL_PARTS, XLenVT, Custom);
1936 case ISD::SHL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 400 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
4587 case ISD::SHL_PARTS:
7609 /// LowerShiftParts - Lower SHL_PARTS/SRA_PARTS/SRL_PARTS, which returns two
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 290 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 491 setOperationAction(ISD::SHL_PARTS, VT, Custom);
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