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    Searched refs:SH_MEM_CONFIG (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik_sdma.c 976 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
cikd.h 1173 #define SH_MEM_CONFIG 0x8C34
radeon_cik.c 5534 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);
5738 radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 3687 uint32_t sh_mem_config; local
3698 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3709 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3788 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3789 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3790 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3795 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3796 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3797 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
amdgpu_gfx_v7_0.c 1866 uint32_t sh_mem_config; local
1876 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1878 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1883 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1964 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1966 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1968 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1970 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
amdgpu_gfx_v9_0.c 2405 uint32_t sh_mem_config; local
2416 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
2424 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
2494 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2496 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2501 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2503 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

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