| /src/external/gpl3/gcc/dist/libgcc/config/pa/ |
| fptr.c | 47 #define SIGN_EXTEND(VAL,BITS) \
135 iptr += SIGN_EXTEND (GET_FIELD (*iptr, 19, 28) |
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/pa/ |
| fptr.c | 47 #define SIGN_EXTEND(VAL,BITS) \
135 iptr += SIGN_EXTEND (GET_FIELD (*iptr, 19, 28) |
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 1484 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1488 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 },
1489 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 },
1490 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 },
1491 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 },
1492 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 },
1493 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
1494 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
1495 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1496 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 441 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
443 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
445 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
447 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
449 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1},
451 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1},
459 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
461 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
463 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
468 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1}
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/nds32/ |
| nds32-relax-opt.cc | 110 || (GET_CODE (mem_src) == SIGN_EXTEND))
142 || (GET_CODE (mem_src) == SIGN_EXTEND))
180 || (GET_CODE (mem_src) == SIGN_EXTEND))
|
| nds32-cost.cc | 245 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
359 case SIGN_EXTEND:
|
| /src/external/gpl3/gcc.old/dist/gcc/config/nds32/ |
| nds32-relax-opt.cc | 110 || (GET_CODE (mem_src) == SIGN_EXTEND))
142 || (GET_CODE (mem_src) == SIGN_EXTEND))
180 || (GET_CODE (mem_src) == SIGN_EXTEND))
|
| nds32-cost.cc | 245 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
359 case SIGN_EXTEND:
|
| /src/external/gpl3/gcc/dist/gcc/config/riscv/ |
| riscv-shorten-memrefs.cc | 86 if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND)
|
| /src/external/gpl3/gcc.old/dist/gcc/config/riscv/ |
| riscv-shorten-memrefs.cc | 85 if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND)
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGAddressAnalysis.cpp | 259 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
271 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
|
| /src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| rs6000-pcrel-opt.cc | 260 if (GET_CODE (mem) == SIGN_EXTEND && GET_MODE (XEXP (mem, 0)) == SImode)
269 else if (GET_CODE (mem) == SIGN_EXTEND
|
| /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| rs6000-pcrel-opt.cc | 260 if (GET_CODE (mem) == SIGN_EXTEND && GET_MODE (XEXP (mem, 0)) == SImode)
269 else if (GET_CODE (mem) == SIGN_EXTEND
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 714 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
716 SIGN_EXTEND,
|
| /src/external/gpl3/gcc/dist/gcc/config/mmix/ |
| mmix.h | 778 gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
780 #define LOAD_EXTEND_OP(MODE) (TARGET_ZERO_EXTEND ? ZERO_EXTEND : SIGN_EXTEND)
|
| /src/external/gpl3/gcc/dist/gcc/ |
| ree.cc | 274 if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
342 if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
747 while (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND)
815 for example have been changed from a (sign_extend (reg))
816 into (zero_extend (sign_extend (reg))).
1109 && (code == SIGN_EXTEND || code == ZERO_EXTEND)
|
| loop-iv.cc | 150 return SIGN_EXTEND;
694 case SIGN_EXTEND:
795 if (prev_code == SIGN_EXTEND)
801 case SIGN_EXTEND:
807 *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
985 case SIGN_EXTEND:
1030 case SIGN_EXTEND:
2191 iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2202 iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
|
| fwprop.cc | 623 ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN
695 /* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG
697 operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will
702 A: (set (reg:DI X) (sign_extend:DI (reg:SI Y)))
714 || GET_CODE (src) == SIGN_EXTEND)
740 && GET_CODE (src) != SIGN_EXTEND)
|
| rtl.def | 573 The machine modes of the operand and of the SIGN_EXTEND expression
575 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
|
| /src/external/gpl3/gcc.old/dist/gcc/config/mmix/ |
| mmix.h | 787 gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
789 #define LOAD_EXTEND_OP(MODE) (TARGET_ZERO_EXTEND ? ZERO_EXTEND : SIGN_EXTEND)
|
| /src/external/gpl3/gcc.old/dist/gcc/config/tilegx/ |
| tilegx.h | 359 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| ree.cc | 274 if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
342 if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
747 while (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND)
815 for example have been changed from a (sign_extend (reg))
816 into (zero_extend (sign_extend (reg))).
1109 && (code == SIGN_EXTEND || code == ZERO_EXTEND)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 644 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
646 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
650 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
652 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
654 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.h | 377 return ISD::SIGN_EXTEND;
381 return ISD::SIGN_EXTEND;
|
| /src/external/gpl3/gcc/dist/gcc/config/cris/ |
| cris.cc | 803 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
1103 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
1105 if (GET_CODE (operand) != SIGN_EXTEND
1116 putc (GET_CODE (operand) == SIGN_EXTEND
1124 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
1538 || (GET_CODE (x) == SIGN_EXTEND
1629 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
2060 case ZERO_EXTEND: case SIGN_EXTEND:
2239 if (GET_CODE (val_rtx) == SIGN_EXTEND
|
