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    Searched refs:SIGN_EXTEND (Results 1 - 25 of 142) sorted by relevancy

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  /src/external/gpl3/gcc.old/dist/libgcc/config/pa/
fptr.c 47 #define SIGN_EXTEND(VAL,BITS) \
135 iptr += SIGN_EXTEND (GET_FIELD (*iptr, 19, 28) |
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 1484 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1488 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 },
1489 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 },
1490 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 },
1491 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 },
1492 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 },
1493 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
1494 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
1495 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1496 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 441 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
443 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
445 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
447 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
449 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1},
451 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1},
459 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
461 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
463 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
468 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1}
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/config/nds32/
nds32-relax-opt.cc 110 || (GET_CODE (mem_src) == SIGN_EXTEND))
142 || (GET_CODE (mem_src) == SIGN_EXTEND))
180 || (GET_CODE (mem_src) == SIGN_EXTEND))
nds32-cost.cc 245 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
359 case SIGN_EXTEND:
nds32-predicates.cc 444 || (GET_CODE (mem_src) == SIGN_EXTEND))
  /src/external/gpl3/gcc.old/dist/gcc/config/riscv/
riscv-shorten-memrefs.cc 85 if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND)
riscv.h 256 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGAddressAnalysis.cpp 259 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
271 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
  /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
rs6000-pcrel-opt.cc 260 if (GET_CODE (mem) == SIGN_EXTEND && GET_MODE (XEXP (mem, 0)) == SImode)
269 else if (GET_CODE (mem) == SIGN_EXTEND
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 714 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
716 SIGN_EXTEND,
  /src/external/gpl3/gcc.old/dist/gcc/config/mmix/
mmix.h 787 gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
789 #define LOAD_EXTEND_OP(MODE) (TARGET_ZERO_EXTEND ? ZERO_EXTEND : SIGN_EXTEND)
  /src/external/gpl3/gcc.old/dist/gcc/config/tilegx/
tilegx.h 359 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
  /src/external/gpl3/gcc.old/dist/gcc/
ree.cc 274 if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
342 if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
747 while (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND)
815 for example have been changed from a (sign_extend (reg))
816 into (zero_extend (sign_extend (reg))).
1109 && (code == SIGN_EXTEND || code == ZERO_EXTEND)
fwprop.cc 618 ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN
690 /* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG
692 operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will
697 A: (set (reg:DI X) (sign_extend:DI (reg:SI Y)))
709 || GET_CODE (src) == SIGN_EXTEND)
735 && GET_CODE (src) != SIGN_EXTEND)
loop-iv.cc 150 return SIGN_EXTEND;
694 case SIGN_EXTEND:
774 case SIGN_EXTEND:
780 *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
958 case SIGN_EXTEND:
1003 case SIGN_EXTEND:
2207 iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2218 iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
rtl.def 573 The machine modes of the operand and of the SIGN_EXTEND expression
575 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
simplify-rtx.cc 631 || GET_CODE (op) == SIGN_EXTEND)
668 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
679 && GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
703 || GET_CODE (XEXP (op, 0)) == SIGN_EXTEND)
817 && (GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
1184 return simplify_gen_unary (SIGN_EXTEND, int_mode, temp, inner);
1392 if (GET_CODE (op) == SIGN_EXTEND
1426 case SIGN_EXTEND:
1454 /* (float (sign_extend <X>)) = (float <X>). */
1455 if (GET_CODE (op) == SIGN_EXTEND)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 644 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
646 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
650 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
652 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
654 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.h 377 return ISD::SIGN_EXTEND;
381 return ISD::SIGN_EXTEND;
  /src/external/gpl3/gcc.old/dist/gcc/config/cris/
cris.cc 799 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
1099 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
1101 if (GET_CODE (operand) != SIGN_EXTEND
1112 putc (GET_CODE (operand) == SIGN_EXTEND
1120 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
1518 || (GET_CODE (x) == SIGN_EXTEND
1602 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
2004 case ZERO_EXTEND: case SIGN_EXTEND:
2183 if (GET_CODE (val_rtx) == SIGN_EXTEND
  /src/external/gpl3/gcc.old/dist/gcc/config/alpha/
alpha.h 799 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
  /src/external/gpl3/gcc.old/dist/gcc/config/rx/
rx.h 182 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
  /src/external/gpl3/gcc.old/dist/gcc/config/v850/
v850.h 740 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
  /src/external/gpl3/gcc.old/dist/gcc/config/loongarch/
loongarch.h 319 (TARGET_64BIT && ((MODE) == SImode || (MODE) == FCCmode) ? SIGN_EXTEND \

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