| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 732 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
737 SIGN_EXTEND_INREG,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
166 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
173 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal)
[all...] |
| AMDGPUISelLowering.cpp | 1239 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1277 case ISD::SIGN_EXTEND_INREG:
1279 // sign_extend_inreg is the one to check for custom lowering. The extended
1756 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1757 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
2765 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
4027 // This is a sign_extend_inreg. Replace it to take advantage of existing
4033 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
|
| SIISelLowering.cpp | 212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
217 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
219 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
821 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
7997 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad
[all...] |
| AMDGPUISelDAGToDAG.cpp | 862 case ISD::SIGN_EXTEND_INREG:
2215 case ISD::SIGN_EXTEND_INREG: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
181 "Unhandled target sign_extend_inreg.");
758 case ISD::SIGN_EXTEND_INREG:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
237 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action);
240 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
1196 case ISD::SIGN_EXTEND_INREG:
1199 // SIGN_EXTEND_INREG, but for non-vector sign extends the result might be an
1250 case ISD::SIGN_EXTEND_INREG:
1670 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract,
1699 // (sign_extend_inreg (extract_vector_elt $indices, $i))
1707 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG)
1995 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 161 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom);
237 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
240 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
1277 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy,
1786 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2091 case ISD::SIGN_EXTEND_INREG:
|
| HexagonISelLowering.cpp | 1502 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1687 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1688 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1689 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
|
| HexagonISelDAGToDAG.cpp | 1459 case ISD::SIGN_EXTEND_INREG: {
1527 case ISD::SIGN_EXTEND_INREG:
1603 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
987 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
1241 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 387 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
391 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
392 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
393 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
4558 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 266 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
287 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
|
| LegalizeVectorOps.cpp | 107 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
435 case ISD::SIGN_EXTEND_INREG:
739 case ISD::SIGN_EXTEND_INREG:
|
| SelectionDAGDumper.cpp | 336 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
|
| LegalizeIntegerTypes.cpp | 88 case ISD::SIGN_EXTEND_INREG:
669 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1025 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1112 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1390 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1803 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
2099 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3859 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3873 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
3885 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi
[all...] |
| LegalizeDAG.cpp | 759 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
931 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1024 case ISD::SIGN_EXTEND_INREG: {
2790 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2887 case ISD::SIGN_EXTEND_INREG: {
2895 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
|
| DAGCombiner.cpp | 1245 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1257 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1675 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
2689 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3531 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
5875 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
8549 TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
8551 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
10275 // possible further transform to sign_extend_inreg.i.e.
10282 // t4: i64 = sign_extend_inreg t
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 552 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
554 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
1857 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
2072 case ISD::SIGN_EXTEND_INREG:
3412 case ISD::SIGN_EXTEND_INREG:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 226 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
526 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
820 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
1245 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1247 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1248 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1249 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1493 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1494 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1495 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 1252 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
983 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1339 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand)
[all...] |
