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    Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 750 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
759 SIGN_EXTEND_VECTOR_INREG,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 117 /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
437 case ISD::SIGN_EXTEND_VECTOR_INREG:
745 case ISD::SIGN_EXTEND_VECTOR_INREG:
SelectionDAGDumper.cpp 338 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
LegalizeVectorTypes.cpp 68 case ISD::SIGN_EXTEND_VECTOR_INREG:
420 case ISD::SIGN_EXTEND_VECTOR_INREG:
961 case ISD::SIGN_EXTEND_VECTOR_INREG:
2209 case ISD::SIGN_EXTEND_VECTOR_INREG:
3083 case ISD::SIGN_EXTEND_VECTOR_INREG:
3564 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3690 case ISD::SIGN_EXTEND_VECTOR_INREG:
3706 case ISD::SIGN_EXTEND_VECTOR_INREG:
4662 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp);
TargetLowering.cpp 806 case ISD::SIGN_EXTEND_VECTOR_INREG:
1918 case ISD::SIGN_EXTEND_VECTOR_INREG: {
1923 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
2777 case ISD::SIGN_EXTEND_VECTOR_INREG:
DAGCombiner.cpp 1676 case ISD::SIGN_EXTEND_VECTOR_INREG:
10256 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
10322 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
11847 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ||
11860 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)))
11861 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00);
20632 Opcode != ISD::SIGN_EXTEND_VECTOR_INREG &&
LegalizeIntegerTypes.cpp 118 case ISD::SIGN_EXTEND_VECTOR_INREG:
4849 case ISD::SIGN_EXTEND_VECTOR_INREG:
SelectionDAG.cpp 3266 case ISD::SIGN_EXTEND_VECTOR_INREG: {
3812 case ISD::SIGN_EXTEND_VECTOR_INREG: {
4933 case ISD::SIGN_EXTEND_VECTOR_INREG:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 100 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 811 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 1065 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1066 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1067 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1379 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
2039 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
6345 case ISD::SIGN_EXTEND_VECTOR_INREG:
6361 case ISD::SIGN_EXTEND_VECTOR_INREG:
6362 return ISD::SIGN_EXTEND_VECTOR_INREG;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 381 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
5475 case ISD::SIGN_EXTEND_VECTOR_INREG:
5788 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||

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