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    Searched refs:SLW (Results 1 - 14 of 14) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/sim/cr16/
simops.c 4043 SLW (addr, a);
4054 SLW (addr, a);
4070 SLW (addr, a);
4081 SLW (addr, a);
4092 SLW (addr, a);
4103 SLW (addr, a);
4114 SLW (addr, a);
4125 SLW (addr, a);
4136 SLW (addr, a);
4147 SLW (addr, a)
    [all...]
cr16-sim.h 385 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
  /src/external/gpl3/gdb/dist/sim/cr16/
simops.c 4043 SLW (addr, a);
4054 SLW (addr, a);
4070 SLW (addr, a);
4081 SLW (addr, a);
4092 SLW (addr, a);
4103 SLW (addr, a);
4114 SLW (addr, a);
4125 SLW (addr, a);
4136 SLW (addr, a);
4147 SLW (addr, a)
    [all...]
cr16-sim.h 385 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativePPC_32.c 210 return push_inst(compiler, SLW | RC(flags) | S(src1) | A(dst) | B(src2));
sljitNativePPC_64.c 342 return push_inst(compiler, ((flags & ALT_FORM2) ? SLW : SLD) | RC(flags) | S(src1) | A(dst) | B(src2));
sljitNativePPC_common.c 206 #define SLW (HI(31) | LO(24))
  /src/external/gpl3/gdb/dist/sim/d10v/
d10v-sim.h 461 #define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
simops.c 3470 SLW (buf+16, host_stat.st_size);
3471 SLW (buf+20, host_stat.st_atime);
3472 SLW (buf+28, host_stat.st_mtime);
3473 SLW (buf+36, host_stat.st_ctime);
  /src/external/gpl3/gdb.old/dist/sim/d10v/
d10v-sim.h 461 #define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
simops.c 3470 SLW (buf+16, host_stat.st_size);
3471 SLW (buf+20, host_stat.st_atime);
3472 SLW (buf+28, host_stat.st_mtime);
3473 SLW (buf+36, host_stat.st_ctime);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 2375 // for instructions that are 32-bit in nature (like slw for example).
3919 case PPC::SLW:
3953 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
4953 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec ||
5135 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
PPCISelLowering.cpp 11244 // slw incr2, incr, shift
11246 // slw mask, mask2, shift
11288 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
11297 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
12250 // slw newval2, newval, shift
12251 // slw oldval2, oldval,shift
12253 // slw mask, mask2, shift
12302 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
12305 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
12316 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg
    [all...]
PPCISelDAGToDAG.cpp 6649 // SLW and SRW always clear the higher-order bits.
6650 if (Op32.getMachineOpcode() == PPC::SLW ||
6863 case PPC::SLW: NewOpcode = PPC::SLW8; break;

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